OTP_CTRL Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	79.781us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.510s	179.391us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.300s	540.797us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	17.270s	7.750ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.300s	3.080ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.310s	1.634ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.300s	540.797us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	3.080ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.380s	68.135us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	69.132us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.230s	2.410ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.330s	2.378ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	51.220s	23.116ms	10	10	100.00
		otp_ctrl_check_fail	1.027m	8.238ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.240s	4.539ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.060m	24.789ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	47.570s	11.281ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	47.220s	2.974ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	54.750s	9.397ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	43.430s	11.955ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.100m	45.464ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.200s	545.665us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.290s	302.750us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.240s	2.390ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.240s	2.390ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.510s	179.391us	5	5	100.00
		otp_ctrl_csr_rw	2.300s	540.797us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	3.080ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.190s	2.101ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.510s	179.391us	5	5	100.00
		otp_ctrl_csr_rw	2.300s	540.797us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	3.080ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.190s	2.101ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.340s	20.175ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.340s	20.175ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_macro_errs	54.750s	9.397ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_macro_errs	54.750s	9.397ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.900s	1.117ms	200	200	100.00
		otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.330s	2.378ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.027m	8.238ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.027m	13.413ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.504m	12.768ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.240s	4.539ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.910s	1.810ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	54.750s	9.397ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	24.600s	6.893ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.044h	1.585s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1321	1343	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.84	93.73	96.55	95.59	91.41	96.96	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.61871106636108636132289704561790523685276219455588215839925273734779478484041
    Line 65951, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70186402534 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 70186402534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.otp_ctrl_stress_all_with_rand_reset.63398782224575492527108776055913579733982735454945920326190082947126777495185
    Line 14567, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5649898687 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 5649898687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.63044945231402696051913076243080803995917672484029763385368079068556891365840
    Line 471, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53743790163 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (493886775 [0x1d701d37] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 53743790163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.otp_ctrl_stress_all_with_rand_reset.12247332802368588782775411684446301093070304230810165486405429096790873788341
    Line 39413, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 143066125911 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1774185178 [0x69bfeada] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 143066125911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.39308777313367466073637548078341020181698607648453019292446458143887127181316
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 103749063 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 103749063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 54.otp_ctrl_stress_all_with_rand_reset.23717404007530223091884330887674446044887921194247811076182407549534934604403
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 426590575 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 426590575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

73.otp_ctrl_stress_all_with_rand_reset.59077409155321333189353350371644184039273880958840097235428115843745190316754
Line 9391, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 127672023177 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 127673689847 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 127675023183 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 127684023201 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 127684189868 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

90.otp_ctrl_stress_all_with_rand_reset.81026879792133067391403304829515099208214771894263762726201728057815373156971
Line 3660, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 26022427671 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 26022611008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 26022627675 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 26022894347 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 26022911014 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.13227506810239041124210441818767165017484812860101952094175742112975897894591
    Line 2582, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27673764340 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 320 [0x140]) dai addr 140 rdata0 readout mismatch
  UVM_INFO @ 27673764340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=382) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.45795251100683858933440861922209298917503139964934274260086668267112705547781
    Line 29759, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 193641965994 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xef0f1010, Comparison=CompareOpEq, exp_data=0x1, call_count=382)
  UVM_INFO @ 193641965994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```