OTP_CTRL Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.000s	738.005us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.750s	1.528ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.950s	595.606us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.860s	5.573ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.950s	77.970us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.100s	1.599ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.950s	595.606us	20	20	100.00
		otp_ctrl_csr_aliasing	4.950s	77.970us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.800s	559.566us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	102.463us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.810s	1.133ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.490s	2.719ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	44.130s	8.364ms	10	10	100.00
		otp_ctrl_check_fail	1.186m	7.301ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.850s	5.142ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	43.240s	1.507ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.770s	2.648ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.538m	25.208ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.016m	8.028ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.064m	27.481ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.462m	44.045ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.240s	603.716us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.120s	310.578us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.940s	583.468us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.940s	583.468us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.750s	1.528ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	595.606us	20	20	100.00
		otp_ctrl_csr_aliasing	4.950s	77.970us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.840s	1.102ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.750s	1.528ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	595.606us	20	20	100.00
		otp_ctrl_csr_aliasing	4.950s	77.970us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.840s	1.102ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
		otp_ctrl_tl_intg_err	20.010s	1.325ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	20.010s	1.325ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_macro_errs	1.016m	8.028ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_macro_errs	1.016m	8.028ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.220s	1.242ms	200	200	100.00
		otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.490s	2.719ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.186m	7.301ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.483m	10.302ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.913m	23.119ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.850s	5.142ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.310s	2.084ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.016m	8.028ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.350s	3.008ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.279h	2.890s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.86	93.79	96.25	95.51	91.89	97.05	96.34	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.33849536912065338527695300794478225644558747848295376606368647267655622393793
    Line 16020, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17929213505 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17929213505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otp_ctrl_stress_all_with_rand_reset.42986476887183046810108260080413898595833402840412146107025470043079150562044
    Line 13784, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53217447508 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 53217447508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.88991638171961606919688568540978331263594802752569636305600143923471629109334
    Line 9321, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14728546024 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (846153030 [0x326f4546] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 14728546024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.otp_ctrl_stress_all_with_rand_reset.107456598339095610018264060682945656182828010977186483671106306128123604905022
    Line 40719, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27260276875 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3799931571 [0xe27e5ab3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 27260276875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 72.otp_ctrl_stress_all_with_rand_reset.60391784391569745388762786614411828527893549460162135766023520030703541418031
    Line 480, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53992262160 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 660 [0x294]) dai addr 294 rdata0 readout mismatch
  UVM_INFO @ 53992262160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.otp_ctrl_stress_all_with_rand_reset.53259629285249400742293189608007441780202580290211943403535994436078223371229
    Line 60873, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44569018238 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 635172657 [0x25dbf731]) dai addr 788 rdata0 readout mismatch
  UVM_INFO @ 44569018238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.otp_ctrl_stress_all_with_rand_reset.110290630667439303895801173691627572157192461998972429048564599779037315203705
    Line 54716, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1207789845707 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 1207789845707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 88.otp_ctrl_stress_all_with_rand_reset.41857559802611721959145755376201814380080495239991457062630542371433025947074
    Line 40444, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69926670192 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 69926670192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

96.otp_ctrl_stress_all_with_rand_reset.3550150222053587968589999050465919312127128836613836430944276345502856622578
Line 7619, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 959616398464 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 959618731802 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 959618898469 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 959624231813 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 959624398480 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1