OTP_CTRL Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.650s	778.672us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.880s	1.519ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.950s	169.330us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.590s	2.027ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.710s	780.384us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.090s	1.664ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.950s	169.330us	20	20	100.00
		otp_ctrl_csr_aliasing	7.710s	780.384us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	38.798us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.480s	134.043us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.030s	1.621ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.540s	3.162ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	49.920s	25.243ms	10	10	100.00
		otp_ctrl_check_fail	57.600s	16.667ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.520s	499.714us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.091m	14.660ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.780s	13.617ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.023m	15.380ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	54.140s	16.338ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	47.110s	2.715ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.244m	78.951ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.450s	608.900us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.920s	753.152us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.710s	2.802ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.710s	2.802ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.880s	1.519ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	169.330us	20	20	100.00
		otp_ctrl_csr_aliasing	7.710s	780.384us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	464.471us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.880s	1.519ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	169.330us	20	20	100.00
		otp_ctrl_csr_aliasing	7.710s	780.384us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	464.471us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
		otp_ctrl_tl_intg_err	47.150s	20.178ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	47.150s	20.178ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_macro_errs	54.140s	16.338ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_macro_errs	54.140s	16.338ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.520s	1.201ms	200	200	100.00
		otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.540s	3.162ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	57.600s	16.667ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.020m	21.558ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.408m	10.864ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.520s	499.714us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.430s	1.571ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	54.140s	16.338ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.420s	3.449ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.085h	576.068ms	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.01	93.81	96.62	95.83	91.89	97.24	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.67729760961653178539026952314752452869814961289661084074041693665325486440083
    Line 4395, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6983901721 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 6983901721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.otp_ctrl_stress_all_with_rand_reset.22646750013876146420051673090208587026851262198048133617572776517796477832896
    Line 71114, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17518931263 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17518931263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.10046788954385357707159706585641149284335759482528584544547899491828505231369
    Line 10891, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1466960275 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (638489914 [0x260e953a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1466960275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.otp_ctrl_stress_all_with_rand_reset.58532131468830907921610451123183852338598154227207464191728470490141171410798
    Line 5282, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 138671800667 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2286612174 [0x884aeece] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 138671800667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

1.otp_ctrl_stress_all_with_rand_reset.70764677387093611591217266933060826769176397665886216953552130823279809433464
Line 16388, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 8705238931 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 8790970729 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8791047653 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8791393811 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8791393811 ps: (dv_base_reg.sv:332) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          0 val

49.otp_ctrl_stress_all_with_rand_reset.111111863928952567378031452765615675401106547322996801841782503719012568590812
Line 9625, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 147536059559 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 147536309561 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 147536392895 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 147538934582 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 147539059583 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=514) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.60936174000771219985751854483789004169390996367308790626716377757723331240695
    Line 25895, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 277594094669 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xe943e010, Comparison=CompareOpEq, exp_data=0x0, call_count=514)
  UVM_INFO @ 277594094669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=167) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.110994616563708232632176997332281267127271286667714610782696982638866544602877
    Line 28941, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25243075899 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x6ccfd010, Comparison=CompareOpEq, exp_data=0x0, call_count=167)
  UVM_INFO @ 25243075899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.otp_ctrl_stress_all_with_rand_reset.77421479537386969546511491809272058263377546277260716318556836637547118150008
    Line 102848, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 510795094528 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 510795094528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 53.otp_ctrl_stress_all_with_rand_reset.89576881579962551424022538508500179860501048956215120198191837020661418234113
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26580477 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26580477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=886) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.61549968866245071596746270754306637714383192851652220040246108837894661052977
    Line 51972, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 272667191838 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x6d20f010, Comparison=CompareOpEq, exp_data=0x0, call_count=886)
  UVM_INFO @ 272667191838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```