OTP_CTRL Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.840s	98.107us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	200.855us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.360s	691.621us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.010s	416.858us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.940s	177.096us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.230s	291.308us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.360s	691.621us	20	20	100.00
		otp_ctrl_csr_aliasing	5.940s	177.096us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.430s	50.684us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.410s	140.998us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.170s	1.088ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.220s	3.335ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	43.590s	26.455ms	10	10	100.00
		otp_ctrl_check_fail	1.931m	13.785ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.240s	4.620ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	54.860s	23.306ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.420s	966.820us	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	48.340s	6.191ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.534m	31.911ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.101m	25.966ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	11.708m	51.622ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.730s	565.993us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.570s	294.491us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.770s	2.156ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.770s	2.156ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	200.855us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	691.621us	20	20	100.00
		otp_ctrl_csr_aliasing	5.940s	177.096us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.690s	264.020us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	200.855us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	691.621us	20	20	100.00
		otp_ctrl_csr_aliasing	5.940s	177.096us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.690s	264.020us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.840s	10.428ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.840s	10.428ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_macro_errs	1.534m	31.911ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_macro_errs	1.534m	31.911ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.540s	15.730ms	200	200	100.00
		otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.220s	3.335ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.931m	13.785ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.440s	5.057ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.032ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.240s	4.620ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.300s	1.182ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.534m	31.911ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.140s	7.604ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.189h	724.106ms	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.03	93.81	96.60	96.06	91.89	97.24	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.72194623922386427770565456080034261646889958112302882270892545514564766022494
    Line 7511, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42091192906 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 42091192906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.otp_ctrl_stress_all_with_rand_reset.96526513999091048888242546770824332881529179507736426426229019983824539970513
    Line 36902, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 573135974018 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 573135974018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.otp_ctrl_csr_mem_rw_with_rand_reset.42179990014503371192249509727109634773895669736696941752665333327836858958312
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 238741981 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 238741981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 16.otp_ctrl_csr_mem_rw_with_rand_reset.39315703008303533480383827826846345206947178987854212586246061999119308938431
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  75802270 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  75802270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.112983001819724653581884081979848246455431653416279196230845219440993893714780
    Line 2359, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 115035336781 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 115035336781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.21226473539469740349192489801318320039942089323228715406312868052663262326302
    Line 396, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  30542163 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156203585 [0x94f7a41] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  30542163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.otp_ctrl_stress_all_with_rand_reset.67354567036140129918992838160000375179852704871520912311057571700176110465842
    Line 39791, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65657621313 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3652461465 [0xd9b42399] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 65657621313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=428) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.47938079835252562796187867674752138999199030141433045630337015032115569640099
    Line 35055, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 50914719807 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xb2ad2010, Comparison=CompareOpEq, exp_data=0x1, call_count=428)
  UVM_INFO @ 50914719807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

37.otp_ctrl_stress_all_with_rand_reset.19669988958762935820672819299874142309980953123107605625284515038306695133694
Line 3413, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 38960810393 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 38960970393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 38961010393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 38962250393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 38962290393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 88.otp_ctrl_stress_all_with_rand_reset.103258163941330994241426978153470542957325482773808151116649340938905015437996
    Line 536, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  45257262 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @  45257262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 91.otp_ctrl_stress_all_with_rand_reset.104479175696431641757657387840255002297730382207698744344145129833270334827705
    Line 13798, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 114055408460 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1328635114 [0x4f315cea]) dai addr 750 rdata0 readout mismatch
  UVM_INFO @ 114055408460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```