OTP_CTRL Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	53.179us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.170s	1.552ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.130s	632.512us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.260s	125.814us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.170s	149.610us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.470s	1.652ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.130s	632.512us	20	20	100.00
		otp_ctrl_csr_aliasing	5.170s	149.610us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.490s	81.197us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	86.809us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.050s	640.291us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.650s	2.553ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	57.050s	21.976ms	10	10	100.00
		otp_ctrl_check_fail	1.247m	7.294ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.500s	5.130ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	44.390s	13.119ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	41.170s	11.813ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	53.620s	17.386ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.965m	14.481ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	57.100s	7.069ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.512m	19.704ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.060s	576.693us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.130s	1.014ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.150s	2.494ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.150s	2.494ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.170s	1.552ms	5	5	100.00
		otp_ctrl_csr_rw	2.130s	632.512us	20	20	100.00
		otp_ctrl_csr_aliasing	5.170s	149.610us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.240s	972.344us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.170s	1.552ms	5	5	100.00
		otp_ctrl_csr_rw	2.130s	632.512us	20	20	100.00
		otp_ctrl_csr_aliasing	5.170s	149.610us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.240s	972.344us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
		otp_ctrl_tl_intg_err	40.420s	19.852ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	40.420s	19.852ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_macro_errs	1.965m	14.481ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_macro_errs	1.965m	14.481ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.920s	13.667ms	200	200	100.00
		otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.650s	2.553ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.247m	7.294ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	54.190s	6.940ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.983m	39.742ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.500s	5.130ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.750s	2.240ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.965m	14.481ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.420s	3.009ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.185h	1.784s	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.84	93.81	96.23	95.63	91.41	97.10	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.20254879082236433435774504783005616381046441859521077693031831945062131969490
      Line 88083, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78800892767 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1314905638 [0x4e5fde26] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 78800892767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.otp_ctrl_stress_all_with_rand_reset.3112374565921112213074464838501516232201538233796548557840939382894749377235
      Line 7753, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1164129723 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1328879647 [0x4f35181f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1164129723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 58.otp_ctrl_stress_all_with_rand_reset.66386408732470494403592824942707780457699080147866035898599202539510710756470
      Line 69415, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 741285851849 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 741285851849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 65.otp_ctrl_stress_all_with_rand_reset.105942067752003832550977251115753511815711986208782570272990183409065639349948
      Line 713, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 611925162 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 611925162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.otp_ctrl_stress_all_with_rand_reset.76955159332725966970398524406488603559050112508982093292915603148447181393550
      Line 76985, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 253439810014 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 253439810014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.otp_ctrl_stress_all_with_rand_reset.59633596967201872728750751877336601857448652756421649717609713944906339766584
      Line 26405, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78151282768 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 78151282768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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