OTP_CTRL Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.680s	191.212us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.460s	367.464us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.490s	597.827us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.310s	1.892ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.210s	553.088us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.150s	1.709ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.490s	597.827us	20	20	100.00
		otp_ctrl_csr_aliasing	6.210s	553.088us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.430s	69.650us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.530s	141.495us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.520s	5.101ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.120s	2.214ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	34.800s	12.178ms	10	10	100.00
		otp_ctrl_check_fail	1.493m	11.864ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.770s	3.840ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.180m	27.105ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.110s	10.498ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	56.990s	16.195ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	59.210s	27.386ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	55.690s	27.928ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.221m	71.882ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.990s	553.864us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.010s	991.139us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.560s	773.931us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.560s	773.931us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.460s	367.464us	5	5	100.00
		otp_ctrl_csr_rw	2.490s	597.827us	20	20	100.00
		otp_ctrl_csr_aliasing	6.210s	553.088us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.080s	418.065us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.460s	367.464us	5	5	100.00
		otp_ctrl_csr_rw	2.490s	597.827us	20	20	100.00
		otp_ctrl_csr_aliasing	6.210s	553.088us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.080s	418.065us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
		otp_ctrl_tl_intg_err	41.770s	18.967ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	41.770s	18.967ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_macro_errs	59.210s	27.386ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_macro_errs	59.210s	27.386ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.420s	10.297ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.120s	2.214ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.493m	11.864ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	3.671m	27.871ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.122m	43.197ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.770s	3.840ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.660s	5.962ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	59.210s	27.386ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.360s	6.289ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.219h	350.333ms	75	100	75.00
V3		TOTAL			76	101	75.25
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.86	93.81	96.30	95.62	91.65	97.10	96.34	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 11 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 11 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.86852169231364002429274045655333020462413814885631199411722546569784107637368
    Line 46374, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 775794507202 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1415740773 [0x54627d65] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 775794507202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.74883250935964931181285832304223176106029003763341299229653116758050329462099
    Line 31416, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16242917906 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3849271554 [0xe56f3902] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 16242917906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.88955591797207909044364825038835228850725341362727147639524322793937674791863
    Line 5564, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 62619988651 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 62619988651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.otp_ctrl_stress_all_with_rand_reset.91286124827756836379574948370705086001874968959375746285683063237041756659104
    Line 8641, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32084714922 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 32084714922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.otp_ctrl_stress_all_with_rand_reset.87201423006338210081538082181954427906155632212807143150575782791881157491644
    Line 7914, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26762790879 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
  UVM_INFO @ 26762790879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

33.otp_ctrl_stress_all_with_rand_reset.351646366269837878751244741869455364930574740334351692927399675302844399662
Line 15652, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 6519534084 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 6519989970 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 6520034088 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 6520798800 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 6520901742 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 56.otp_ctrl_stress_all_with_rand_reset.96202578637362620693773873842890075151966609376330784980883452469268690752613
    Line 1604, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19028036705 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 600 [0x258]) dai addr 258 rdata0 readout mismatch
  UVM_INFO @ 19028036705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 72.otp_ctrl_stress_all_with_rand_reset.16427389402812423141564303950673267210941988156787032770637507565289372383939
    Line 23606, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 179846870151 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 179846870151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 77.otp_ctrl_stress_all_with_rand_reset.92009256849683579789420792487723723153798630754630829711118231691208243188680
    Line 16689, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 96746696222 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 96746696222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 81.otp_ctrl_stress_all_with_rand_reset.71610290701928328949856603080947732303615806819527467381271272494190648705381
    Line 48545, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11001760769 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x578c8010, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
  UVM_INFO @ 11001760769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```