OTP_CTRL Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.690s	65.602us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.920s	1.033ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.300s	648.862us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.440s	4.118ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.790s	210.099us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.950s	1.677ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.300s	648.862us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	210.099us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	126.344us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.940s	506.150us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.380s	1.068ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.100s	2.499ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.499m	16.312ms	10	10	100.00
		otp_ctrl_check_fail	1.084m	9.836ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.040s	4.386ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	49.640s	6.851ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.230s	11.543ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	48.930s	5.825ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.223m	7.564ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.056m	32.101ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.170m	33.873ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.040s	577.049us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.130s	260.171us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.010s	3.333ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.010s	3.333ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.920s	1.033ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	648.862us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	210.099us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.560s	1.440ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.920s	1.033ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	648.862us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	210.099us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.560s	1.440ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
		otp_ctrl_tl_intg_err	39.020s	19.050ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.020s	19.050ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_macro_errs	1.223m	7.564ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_macro_errs	1.223m	7.564ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.210s	12.970ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.100s	2.499ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.084m	9.836ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.151m	15.710ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.812ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.040s	4.386ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.930s	1.281ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.223m	7.564ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.920s	3.068ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.156h	180.959ms	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1319	1343	98.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.86	93.79	96.30	95.55	91.65	97.05	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.101876943626446174421635045997029824477684540157418842220011660514428494435703
    Line 4077, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4996340570 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 4996340570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.otp_ctrl_stress_all_with_rand_reset.42142599127031167911565606107919564141783742454101375057208653528319639271027
    Line 34893, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4652034307 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 4652034307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.31515162792250725268575646729253818368214470553094892541413246062045639261819
    Line 84940, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1104235409890 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4004473218 [0xeeaf6982] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1104235409890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.otp_ctrl_stress_all_with_rand_reset.114282703360324720953297389839441317398493124740641684758555193054941644431530
    Line 67711, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59529089145 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4099992910 [0xf460ed4e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 59529089145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.otp_ctrl_csr_mem_rw_with_rand_reset.111817388816760900777110548118826565873955221979920428958941248075233643678982
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 103081346 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 103081346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 14.otp_ctrl_csr_mem_rw_with_rand_reset.7967134313468429442887403011903318701621559090463114056413869889761320281500
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  34250615 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  34250615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 68.otp_ctrl_stress_all_with_rand_reset.41509050548599846208312518463235988049829703542219659794377291853873560183870
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 108601996 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 108601996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

80.otp_ctrl_stress_all_with_rand_reset.95941121756729113282234237988752796329725795549970870873797783013395914700211
Line 55379, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 25986867880 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 25986987880 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 25987057880 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 25987207880 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 25987257880 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

95.otp_ctrl_stress_all_with_rand_reset.16736584298370138089347114932756007504312632826787388171316196469807705469211
Line 25859, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 37038719155 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 37038912703 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 37039009477 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 37061106207 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 37061299755 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 86.otp_ctrl_stress_all_with_rand_reset.62902340734508285196111809683612348205609551816071461928065354719142567930934
    Line 84834, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108426514046 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 108426514046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 87.otp_ctrl_stress_all_with_rand_reset.97127092429437952453500301496548963692723775278807123693089909830530495255293
    Line 6588, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24496657777 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 24496657777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.otp_ctrl_stress_all_with_rand_reset.38372371968554492806648815459937983488706162846520033157395842342574843783430
    Line 29806, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115173219185 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 900 [0x384]) dai addr 384 rdata0 readout mismatch
  UVM_INFO @ 115173219185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 59.otp_ctrl_stress_all_with_rand_reset.85539717590097553708451947719770303917941701653050813562424107280601369185484
    Line 25534, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 160922001646 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 160922001646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```