OTP_CTRL Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.640s	72.344us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.370s	1.442ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.080s	551.507us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	17.250s	6.767ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.040s	602.420us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.380s	101.015us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.080s	551.507us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	602.420us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.000s	507.423us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.510s	71.685us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.880s	1.502ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.340s	2.357ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.220s	14.516ms	10	10	100.00
		otp_ctrl_check_fail	1.295m	10.060ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.430s	4.532ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.203m	14.686ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.160s	11.342ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.490s	22.189ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.330m	34.759ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.510s	5.075ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.062m	33.440ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.120s	621.081us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.960s	790.319us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	11.460s	3.206ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	11.460s	3.206ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.370s	1.442ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	551.507us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	602.420us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.480s	535.419us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.370s	1.442ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	551.507us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	602.420us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.480s	535.419us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.040s	20.112ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.040s	20.112ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_macro_errs	2.330m	34.759ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_macro_errs	2.330m	34.759ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.240s	2.994ms	200	200	100.00
		otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.340s	2.357ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.295m	10.060ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.160m	15.669ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.940m	41.387ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.430s	4.532ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.930s	4.690ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.330m	34.759ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.910s	5.930ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.796m	12.313ms	48	100	48.00
V3		TOTAL			49	101	48.51
		TOTAL			1290	1343	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.89	93.78	96.20	95.67	91.89	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 21 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 21 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.18498981290815898000224920126107178330588503931355234773998834682848440976640
    Line 328, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  37032058 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1960713405 [0x74de1cbd] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  37032058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otp_ctrl_stress_all_with_rand_reset.6965189820109774133266645718739759944372600813764026044860140900682933036255
    Line 69637, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9548210402 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2098731083 [0x7d18184b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_1
  UVM_INFO @ 9548210402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 20 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.92831600482555221641880601192286238191036828267343848168785952356056315566589
    Line 11831, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2229454965 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 2229454965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.13778727711614330186280211060888931563635879474378929670482900921038185194753
    Line 12905, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 336316955 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 336316955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *b* rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.57046713771677770952788938492912443506832647469367571875842317940095625727488
    Line 3118, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1028568313 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 436 [0x1b4]) dai addr 1b4 rdata0 readout mismatch
  UVM_INFO @ 1028568313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.otp_ctrl_stress_all_with_rand_reset.92564175420663334681395458020340429945315555996667823454800988705339168877999
    Line 398, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7204080280 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1456 [0x5b0]) dai addr 5b0 rdata0 readout mismatch
  UVM_INFO @ 7204080280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.7733889232077322284616535711133488970225701624849688584080987551148629895973
    Line 3794, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 529194993 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 529194993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.otp_ctrl_stress_all_with_rand_reset.68591533961061353753888696877741692928967351464641282732024441919632423073614
    Line 21782, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2586804003 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 2586804003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:848) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.74211928270724847062260591865559450898985476076911743858174397001154568495540
    Line 29356, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36036458885 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36036458885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.otp_ctrl_stress_all_with_rand_reset.83425486434245040679909628423029940048374896804281524878660735433839634632442
    Line 12258, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25099462330 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25099462330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.61150116700165039185657591594382262302496315824076994709065736057460343045069
    Line 4238, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 871084478 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 871084478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 98.otp_ctrl_stress_all_with_rand_reset.109399177937577799760348810902842247895483363285190010402656294297849223879963
    Line 15775, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3323157924 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 3323157924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.otp_ctrl_csr_mem_rw_with_rand_reset.39094262078339947283275535183566633704285987657321468116668081358349847605968
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  68496073 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  68496073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.otp_ctrl_stress_all_with_rand_reset.66678208829394866194028468243361332306576749102395760950864188256119197202046
    Line 17554, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14057697230 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2064354649 [0x7b0b8d59]) dai addr 6d4 rdata0 readout mismatch
  UVM_INFO @ 14057697230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 63.otp_ctrl_stress_all_with_rand_reset.21386350107139852000279529775049678949901278553674200046077356890385335863105
    Line 270, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3620641263 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 4212215034 [0xfb114cfa]) dai addr 768 rdata0 readout mismatch
  UVM_INFO @ 3620641263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 75.otp_ctrl_stress_all_with_rand_reset.42117821455077265941468618489865235840454740476085297049539533197868989562085
    Line 36353, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34025404015 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 34025404015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

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GitHub Revision: `c082b8981f`