OTP_CTRL Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	51.732us	1	1	100.00
V1	smoke	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.640s	1.050ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.900s	580.901us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	18.670s	6.970ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.790s	77.491us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.220s	358.296us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.900s	580.901us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	77.491us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.470s	504.080us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.520s	519.824us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.000s	9.902ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.900s	2.599ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	51.010s	23.894ms	10	10	100.00
		otp_ctrl_check_fail	38.300s	12.197ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.590s	4.071ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	43.420s	6.362ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	38.670s	13.156ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	56.460s	17.040ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	51.660s	18.232ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	56.810s	18.269ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	13.018m	133.114ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	595.293us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.340s	467.858us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.550s	375.481us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.550s	375.481us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.640s	1.050ms	5	5	100.00
		otp_ctrl_csr_rw	1.900s	580.901us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	77.491us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.520s	1.238ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.640s	1.050ms	5	5	100.00
		otp_ctrl_csr_rw	1.900s	580.901us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	77.491us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.520s	1.238ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
		otp_ctrl_tl_intg_err	31.750s	20.242ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	31.750s	20.242ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_macro_errs	51.660s	18.232ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_macro_errs	51.660s	18.232ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.210s	13.387ms	200	200	100.00
		otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.900s	2.599ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	38.300s	12.197ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	36.680s	22.318ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.804m	165.597ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.590s	4.071ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	34.180s	11.812ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	51.660s	18.232ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.570s	6.925ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	5.721m	111.064ms	47	100	47.00
V3		TOTAL			48	101	47.52
		TOTAL			1289	1343	95.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.90	93.81	96.18	95.61	91.89	97.10	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 24 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 24 failures.

    • 2.otp_ctrl_stress_all_with_rand_reset.20974372739527341669046503990696618988979139379062666563162434724428834275551
      Line 9190, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2649549865 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3548745771 [0xd385902b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 2649549865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.otp_ctrl_stress_all_with_rand_reset.25538239833073184426567097573122846790700353456531905268763167228284696663209
      Line 5868, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 678080150 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1713046707 [0x661b04b3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 678080150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 24 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 24 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.61945718772831152541908606713489599147562282340220701337014125823141021775343
      Line 18692, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3938525232 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 3938525232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.otp_ctrl_stress_all_with_rand_reset.44403462188222749935406973972537069778738554560161759704373629448063629151772
      Line 20023, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5835362794 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 5835362794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 12.otp_ctrl_stress_all_with_rand_reset.69720974963887588746211738200847355124938503059955098514248081327122023241969
      Line 14821, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6684517715 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 268 [0x10c]) dai addr 10c rdata0 readout mismatch
        UVM_INFO @ 6684517715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.otp_ctrl_stress_all_with_rand_reset.92858275441582177460653458522856323016952290693152790629981407134331773023552
      Line 11897, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14332875264 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 780 [0x30c]) dai addr 30c rdata0 readout mismatch
        UVM_INFO @ 14332875264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 16.otp_ctrl_csr_mem_rw_with_rand_reset.93094829397760429355243703588649869880779694170127429159755586360242955033393
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  26222600 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  26222600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 91.otp_ctrl_stress_all_with_rand_reset.77038547476831552517142560719190278205099539888335942250120343820423318184410
      Line 759, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 158623979 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 158623979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 64.otp_ctrl_stress_all_with_rand_reset.70254770617104420150390320664107410093118899348051542271431052575078390635329
      Line 2204, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17031436805 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1280 [0x500]) dai addr 500 rdata0 readout mismatch
        UVM_INFO @ 17031436805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 85.otp_ctrl_stress_all_with_rand_reset.98838574068956851277975209477401988313589428551141497064131651635459791915545
      Line 2722, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 435575849 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 435575849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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