584c3d46af| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 2.490s | 120.271us | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 2.440s | 591.771us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 8.080s | 567.160us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 8.270s | 2.560ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 3.950s | 394.294us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.440s | 591.771us | 20 | 20 | 100.00 |
| otp_ctrl_csr_aliasing | 8.270s | 2.560ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 1.400s | 81.522us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 2.000s | 541.434us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 116 | 56.03 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 0 | 1 | 0.00 | ||
| V2 | init_fail | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2 | partition_check | otp_ctrl_background_chks | 0 | 10 | 0.00 | ||
| otp_ctrl_check_fail | 0 | 50 | 0.00 | ||||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | partition_lock | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 0 | 50 | 0.00 | ||
| otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 0 | 50 | 0.00 | ||
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2 | test_access | otp_ctrl_test_access | 0 | 50 | 0.00 | ||
| V2 | stress_all | otp_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | otp_ctrl_intr_test | 2.030s | 575.698us | 50 | 50 | 100.00 |
| V2 | alert_test | otp_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 7.670s | 2.805ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 7.670s | 2.805ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 2.490s | 120.271us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.440s | 591.771us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 8.270s | 2.560ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 4.700s | 1.757ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 2.490s | 120.271us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.440s | 591.771us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 8.270s | 2.560ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 4.700s | 1.757ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1101 | 8.17 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | tl_intg_err | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| otp_ctrl_tl_intg_err | 36.200s | 18.942ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 36.200s | 18.942ms | 20 | 20 | 100.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| V3 | TOTAL | 0 | 101 | 0.00 | |||
| TOTAL | 175 | 1343 | 13.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 7 | 77.78 |
| V2 | 17 | 17 | 3 | 17.65 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 32.44 | 21.33 | 30.22 | 13.29 | 0.00 | 21.73 | 99.69 | 40.81 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 584 failures:
Test otp_ctrl_wake_up has 1 failures.
Test otp_ctrl_partition_walk has 1 failures.
Test otp_ctrl_init_fail has 183 failures.
0.otp_ctrl_init_fail.96704641239955357135194385994676059619807578712195833524594713680072280005586
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest/run.log
1.otp_ctrl_init_fail.111473217590480471776767004965529534977246023521497150890337893254774367438996
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest/run.log
... and 181 more failures.
Test otp_ctrl_parallel_lc_req has 48 failures.
0.otp_ctrl_parallel_lc_req.89043705270024956903942292529604402190248670091699005909385686671047393118421
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest/run.log
1.otp_ctrl_parallel_lc_req.84643194539852016956407707056579379034940729039629619132163346119454195163695
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest/run.log
... and 46 more failures.
Test otp_ctrl_dai_lock has 48 failures.
0.otp_ctrl_dai_lock.56396281399417241345063631928315106268751762924560850694359955077458664574142
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log
1.otp_ctrl_dai_lock.86452185763176058830637735399818856070817385149484168062366027493418726028349
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest/run.log
... and 46 more failures.
... and 12 more tests.
Job killed most likely because its dependent job failed. has 584 failures:
Test otp_ctrl_smoke has 8 failures.
0.otp_ctrl_smoke.48284163634678786455618978411544254116328096307410075691421645763675833230620
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest/run.log
1.otp_ctrl_smoke.59334998745685668838205788228735358185566994678696453477733332685752169951289
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest/run.log
... and 6 more failures.
Test otp_ctrl_low_freq_read has 1 failures.
Test otp_ctrl_background_chks has 8 failures.
0.otp_ctrl_background_chks.54111078797759519636227501906561127655427084635382232545864686637389020842678
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest/run.log
1.otp_ctrl_background_chks.83399362631240742649954883913029046296339875308241975905073460827687841584472
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest/run.log
... and 6 more failures.
Test otp_ctrl_parallel_lc_esc has 173 failures.
0.otp_ctrl_parallel_lc_esc.6525253384435470288112967424992178124419971310310386219952355822036529173124
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest/run.log
1.otp_ctrl_parallel_lc_esc.33663997324850801660542861318419687110618923939892723054411304025839991909057
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest/run.log
... and 171 more failures.
Test otp_ctrl_dai_errs has 48 failures.
0.otp_ctrl_dai_errs.18568937541756085968362452747384421987302108562344398398971577053053404076830
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log
1.otp_ctrl_dai_errs.109581807828146550765539108666830668450681505481321053022443512818613670584247
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest/run.log
... and 46 more failures.
... and 12 more tests.