OTP_CTRL Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	99.134us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.660s	958.550us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.310s	562.407us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.140s	5.536ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.400s	1.208ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.170s	1.644ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.310s	562.407us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	1.208ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.470s	52.288us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.530s	131.879us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.040s	1.473ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.290s	2.622ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.580s	1.498ms	10	10	100.00
		otp_ctrl_check_fail	48.600s	6.129ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.380s	3.688ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.630s	2.675ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.130s	12.357ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	53.390s	15.208ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	54.320s	25.916ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	3.966m	61.066ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.570m	34.356ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.290s	602.277us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.870s	624.764us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.500s	666.156us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.500s	666.156us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.660s	958.550us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	562.407us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	1.208ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.810s	1.835ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.660s	958.550us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	562.407us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	1.208ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.810s	1.835ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.460s	19.105ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.460s	19.105ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_macro_errs	54.320s	25.916ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_macro_errs	54.320s	25.916ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.520s	11.728ms	200	200	100.00
		otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.290s	2.622ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	48.600s	6.129ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.982m	14.479ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.888m	173.512ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.380s	3.688ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.920s	6.031ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	54.320s	25.916ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.350s	3.409ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.875m	62.271ms	52	100	52.00
V3		TOTAL			53	101	52.48
		TOTAL			1295	1343	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.97	93.81	96.15	95.68	92.36	97.10	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 20 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.22981562743109135330230403923863803003863018611685942028014017163850447707437
      Line 4224, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8337676948 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 8337676948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.otp_ctrl_stress_all_with_rand_reset.3737183207845697536482890107223477632370335228466079829853765481249559850358
      Line 914, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1312231468 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1312231468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 19 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 19 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.96805057662299084816610523238106934713940345196996808738831170170577962561542
      Line 52744, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40090332734 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1832997354 [0x6d4151ea] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 40090332734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.otp_ctrl_stress_all_with_rand_reset.72210924045689544579529502616338408814294815593872075472581383153000400030608
      Line 1456, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 185406325 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1552786520 [0x5c8da458] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 185406325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 5 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 26.otp_ctrl_stress_all_with_rand_reset.69572419073162861139198203671447166235375245787177331881573955790614393216100
      Line 5943, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27371127337 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 27371127337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.otp_ctrl_stress_all_with_rand_reset.1890606221389315319790549699507068419795744274225530335196656551264340771370
      Line 57691, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2703796409 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 2703796409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 3 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.otp_ctrl_stress_all_with_rand_reset.77652791104443177238654134987281451309356056579095861712939693039449273897796
      Line 270, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3491606902 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3789884412 [0xe1e50bfc]) dai addr 730 rdata0 readout mismatch
        UVM_INFO @ 3491606902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 56.otp_ctrl_stress_all_with_rand_reset.79594611984742161705686519011431182878941937959894279382429703761064655628364
      Line 1032, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11498614601 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1328 [0x530]) dai addr 530 rdata0 readout mismatch
        UVM_INFO @ 11498614601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 71.otp_ctrl_stress_all_with_rand_reset.56703360285461045345726757334027966970248676869511816318519700093286033451264
      Line 5771, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10427070320 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10427070320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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