OTP_CTRL Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.780s	70.969us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.760s	197.728us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.840s	87.814us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.080s	6.848ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.460s	639.418us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.910s	413.640us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.840s	87.814us	20	20	100.00
		otp_ctrl_csr_aliasing	6.460s	639.418us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.940s	546.576us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.390s	42.098us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.500s	632.245us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.670s	2.413ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.860s	2.745ms	10	10	100.00
		otp_ctrl_check_fail	2.987m	49.348ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.060s	5.102ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	43.670s	9.720ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.570s	12.601ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.052m	19.359ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.100m	5.763ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	57.100s	6.298ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.280m	238.490ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.300s	547.557us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.710s	347.718us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.920s	2.757ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.920s	2.757ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.760s	197.728us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	87.814us	20	20	100.00
		otp_ctrl_csr_aliasing	6.460s	639.418us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.100s	1.969ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.760s	197.728us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	87.814us	20	20	100.00
		otp_ctrl_csr_aliasing	6.460s	639.418us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.100s	1.969ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
		otp_ctrl_tl_intg_err	36.630s	20.053ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	36.630s	20.053ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_macro_errs	1.100m	5.763ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_macro_errs	1.100m	5.763ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.650s	10.794ms	200	200	100.00
		otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.670s	2.413ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.987m	49.348ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.680s	5.005ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.931m	39.742ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.060s	5.102ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.160s	4.439ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.100m	5.763ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.540s	3.444ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.474m	85.001ms	50	100	50.00
V3		TOTAL			51	101	50.50
		TOTAL			1293	1343	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.82	93.81	96.15	95.75	91.41	97.10	96.34	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 20 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.87563802701086449070124653515280346779811648044832596478458360080346836396365
    Line 1557, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2633870555 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (924326558 [0x37181a9e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_1
  UVM_INFO @ 2633870555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otp_ctrl_stress_all_with_rand_reset.100023430225099448426747209658792521645649220536601496025866051270514449579948
    Line 26144, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1984173290 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3374178070 [0xc91ddf16] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1984173290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 20 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 20 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.81380005545224487437747118267038372497699920156337815730851838671849227593242
    Line 7621, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 859593802 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 859593802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.otp_ctrl_stress_all_with_rand_reset.84213102975595484956614208978921525686903878193770482144860302870265126386885
    Line 5712, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2839046130 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 2839046130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.45919766955781205210061745412445365375555855635920693632894903842385444593856
    Line 6573, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1521556084 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1521556084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 76.otp_ctrl_stress_all_with_rand_reset.87291285567880342871566295594401611339594038565167069346496375024617592945800
    Line 628, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 285051619 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 285051619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 63.otp_ctrl_stress_all_with_rand_reset.64041173770985384975901411375122932806643111950745465793529289565848800879295
    Line 342, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 143587871 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 143587871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 84.otp_ctrl_stress_all_with_rand_reset.97580583382715976072894278904714252936593303592829520539123828702817005781042
    Line 876, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153373446 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 153373446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.43392832086214530811472936248852990653165418842867992997377773412619295122527
    Line 14566, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21401424426 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1096524878 [0x415ba44e]) dai addr 71c rdata0 readout mismatch
  UVM_INFO @ 21401424426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:205) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.101777933910315927887920304281037420066425290676005308276951264577140202895273
    Line 5794, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2226102297 ps: (otp_ctrl_scoreboard.sv:205) [uvm_test_top.env.scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2226102297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 53.otp_ctrl_stress_all_with_rand_reset.64194685020999910192422995561345984782841225548797858698981877857228423476035
    Line 4263, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 854285590 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 854285590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *fc rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 55.otp_ctrl_stress_all_with_rand_reset.87801573736755537654368775627264124254614587188659068977132405880014684132018
    Line 20577, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4145826587 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1532 [0x5fc]) dai addr 5fc rdata0 readout mismatch
  UVM_INFO @ 4145826587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 65.otp_ctrl_stress_all_with_rand_reset.71547276259580299676775455701422918814790873973106997813943665010039654297615
    Line 5383, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 534006326 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 534006326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 92.otp_ctrl_stress_all_with_rand_reset.51117305300174587296058589355264935189676675966844787446198443469654330914097
    Line 16594, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13048123720 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1560 [0x618]) dai addr 618 rdata0 readout mismatch
  UVM_INFO @ 13048123720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

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Coverage Results

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GitHub Revision: `76588857da`