OTP_CTRL Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.690s	118.063us	1	1	100.00
V1	smoke	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.620s	112.182us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.250s	681.677us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.780s	3.023ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.150s	415.023us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.750s	209.279us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.250s	681.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.150s	415.023us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.490s	130.751us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.540s	136.682us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.030s	2.947ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.040s	3.324ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	27.680s	785.787us	10	10	100.00
		otp_ctrl_check_fail	55.210s	5.120ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.770s	5.387ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	59.810s	2.860ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.660s	9.993ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.200s	24.487ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.151m	16.704ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.410s	4.106ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.504m	36.922ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.980s	524.999us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	6.010s	595.822us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.710s	2.200ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.710s	2.200ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.620s	112.182us	5	5	100.00
		otp_ctrl_csr_rw	2.250s	681.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.150s	415.023us	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.160s	2.195ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.620s	112.182us	5	5	100.00
		otp_ctrl_csr_rw	2.250s	681.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.150s	415.023us	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.160s	2.195ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.700s	10.314ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.700s	10.314ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_macro_errs	2.151m	16.704ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_macro_errs	2.151m	16.704ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.930s	16.669ms	200	200	100.00
		otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.040s	3.324ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	55.210s	5.120ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	51.860s	10.768ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.258m	154.636ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.770s	5.387ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	47.690s	4.453ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.151m	16.704ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.000s	3.050ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.056m	10.107ms	54	100	54.00
V3		TOTAL			55	101	54.46
		TOTAL			1296	1343	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.77	93.76	96.25	95.55	91.41	97.00	96.28	93.14

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 23 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.88924356614409382351018411179337491863870612056381268039625790109741104158976
      Line 2151, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1682337553 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1720565961 [0x668dc0c9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1682337553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.otp_ctrl_stress_all_with_rand_reset.110914182899826170621137259005117920258751468298770403323860921692226206815593
      Line 26622, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9486928762 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3954328002 [0xebb241c2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 9486928762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 19 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 19 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.88968643050346202650420435939734170112732108127885931570596115795644641767728
      Line 23415, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7829179742 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 7829179742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.otp_ctrl_stress_all_with_rand_reset.23470484084425880064097058443692759699593761829831727233565710731684746077381
      Line 11914, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2834878982 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 2834878982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 37.otp_ctrl_stress_all_with_rand_reset.36308778067825664465597484759793164291609176040819731408970201832589819931562
      Line 336, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  52123145 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @  52123145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 68.otp_ctrl_stress_all_with_rand_reset.68592639318184759570856862498481298402112642532046607457609527605973534632194
      Line 6676, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1201738316 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 1201738316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:672) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr has 1 failures:

  • Test otp_ctrl_stress_all has 1 failures.

    • 8.otp_ctrl_stress_all.46045735495357381451884235137528551460747124140274508978609972509093659255058
      Line 25480, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7826372020 ps: (otp_ctrl_scoreboard.sv:672) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: OtpErr
        UVM_INFO @ 7826372020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.otp_ctrl_stress_all_with_rand_reset.47787210538597949478996816648955575116446619211781335845221334335826475715598
      Line 31900, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1819572667 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 572 [0x23c]) dai addr 23c rdata0 readout mismatch
        UVM_INFO @ 1819572667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 53.otp_ctrl_stress_all_with_rand_reset.6864390643076659555975865592726562399835710210979939397146606623887410770097
      Line 37758, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20893033378 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1236436168 [0x49b284c8]) dai addr 740 rdata0 readout mismatch
        UVM_INFO @ 20893033378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.08.17_07.15.41
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• 2024.08.15_05.30.47
• 2024.08.14_08.34.37
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