OTP_CTRL Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.780s	56.848us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.700s	1.523ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.260s	635.800us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.410s	350.463us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.090s	344.395us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.450s	1.562ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.260s	635.800us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	344.395us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.870s	520.479us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	55.256us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.110s	870.375us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.680s	2.799ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.253m	12.715ms	10	10	100.00
		otp_ctrl_check_fail	54.620s	7.754ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.930s	4.825ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.570s	5.929ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.490s	13.054ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	43.730s	2.098ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.483m	23.523ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	47.690s	13.018ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.966m	233.231ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.330s	585.939us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.060s	1.002ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.260s	2.602ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.260s	2.602ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.700s	1.523ms	5	5	100.00
		otp_ctrl_csr_rw	2.260s	635.800us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	344.395us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	839.766us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.700s	1.523ms	5	5	100.00
		otp_ctrl_csr_rw	2.260s	635.800us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	344.395us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	839.766us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.220s	5.021ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.220s	5.021ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_macro_errs	1.483m	23.523ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_macro_errs	1.483m	23.523ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.300s	17.577ms	200	200	100.00
		otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.680s	2.799ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.620s	7.754ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.081m	24.360ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.912m	169.884ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.930s	4.825ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.290s	7.725ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.483m	23.523ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.690s	3.427ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.472m	45.299ms	62	100	62.00
V3		TOTAL			63	101	62.38
		TOTAL			1305	1343	97.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.81	96.25	95.57	91.89	97.10	96.34	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 18 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 18 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.19758833055821712995351119093776073683428393113850776445425808032363613755299
    Line 2207, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 577674735 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 577674735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.95604794179177634505831610293398262908404247959758144891946671445175419967828
    Line 28125, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12402258121 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 12402258121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 14 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 14 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.31498888427142672383424827524267051431104618858973597401421237304383790243724
    Line 45113, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6066696082 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2941517526 [0xaf53fed6] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 6066696082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.21728754091614811437499774582159423051245159536023491937491047235461217481206
    Line 12660, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11816791382 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3637959805 [0xd8d6dc7d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 11816791382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.65811995978253152793182839510833571009534559850971091504331233810708057584042
    Line 53072, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15127888217 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15127888217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.otp_ctrl_stress_all_with_rand_reset.113642663548548262592817940818120695388816638950456410845623321197227337758389
    Line 29875, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29520435613 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29520435613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.56577906636690578261885386054612417286220647170210391072219133176370000707224
    Line 476, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  80138745 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @  80138745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 84.otp_ctrl_stress_all_with_rand_reset.88086033933172229830125065449780845986036712150857708954560225278435290127914
    Line 1763, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 532058841 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 532058841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.otp_ctrl_stress_all_with_rand_reset.24545938862805646332138951309457916344398936211372395900906122658867869080676
    Line 36032, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16479842983 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1604 [0x644]) dai addr 644 rdata0 readout mismatch
  UVM_INFO @ 16479842983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

89.otp_ctrl_stress_all_with_rand_reset.62389895088183398986491856852987777964715590003094054111830752061180936255582
Line 2692, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 392165046 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 392275046 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 392285046 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 392745046 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 392775046 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1