OTP_CTRL Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.680s	53.080us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.280s	183.435us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.480s	606.104us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.350s	513.750us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.060s	653.555us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.070s	1.636ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.480s	606.104us	20	20	100.00
		otp_ctrl_csr_aliasing	7.060s	653.555us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.080s	532.742us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.510s	129.572us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.340s	626.909us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.500s	2.119ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	46.840s	25.179ms	10	10	100.00
		otp_ctrl_check_fail	47.300s	4.169ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.270s	4.482ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	55.350s	4.498ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.220s	8.552ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.042m	26.102ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	6.156m	48.721ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.470s	8.583ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.170m	219.643ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.100s	619.467us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.410s	885.266us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.980s	2.954ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.980s	2.954ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.280s	183.435us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	606.104us	20	20	100.00
		otp_ctrl_csr_aliasing	7.060s	653.555us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	140.340us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.280s	183.435us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	606.104us	20	20	100.00
		otp_ctrl_csr_aliasing	7.060s	653.555us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	140.340us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.210s	19.962ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.210s	19.962ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_macro_errs	6.156m	48.721ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_macro_errs	6.156m	48.721ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.150s	13.285ms	200	200	100.00
		otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.500s	2.119ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.300s	4.169ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.212m	35.449ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.743m	14.916ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.270s	4.482ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.250s	2.805ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	6.156m	48.721ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.110s	3.029ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.796m	85.584ms	53	100	53.00
V3		TOTAL			54	101	53.47
		TOTAL			1295	1343	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.79	96.13	95.96	91.65	97.05	96.34	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 24 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.10807675506328193294916630448792177044549708003425274518437928922052115228898
      Line 416, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  69093165 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @  69093165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.otp_ctrl_stress_all_with_rand_reset.105087813612721350984443555346777907863112788798764715557333868695017242656233
      Line 476, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 390725398 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 390725398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 16 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 16 failures.

    • 12.otp_ctrl_stress_all_with_rand_reset.37368634795704765907401342695242638297550962721846725616417042409472812985320
      Line 10868, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6276035433 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2237014683 [0x8556229b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 6276035433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.otp_ctrl_stress_all_with_rand_reset.86409387681919168176533201742374716371499179346335851735278386106450553552754
      Line 17620, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 518406585 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2866746866 [0xaadf15f2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 518406585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.17340119676625569247792402917625948001503175437693694889731024176458498277743
      Line 5132, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17336402542 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1672 [0x688]) dai addr 688 rdata0 readout mismatch
        UVM_INFO @ 17336402542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.otp_ctrl_stress_all_with_rand_reset.23492631913924650069463059007339511811854562819035745306247347780680267714406
      Line 1624, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18132020986 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1332 [0x534]) dai addr 534 rdata0 readout mismatch
        UVM_INFO @ 18132020986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 11.otp_ctrl_csr_mem_rw_with_rand_reset.50303007380650034273817289370923878874620204500771632168245482334621592567822
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 430907847 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 430907847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 77.otp_ctrl_stress_all_with_rand_reset.31990700089082769957918000689106978040316586893433656738463390394809754194533
      Line 9616, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 1131661965 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 1131661965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 78.otp_ctrl_stress_all_with_rand_reset.71115614155165869738332667523925634052854336473191568195550684775810346502852
      Line 399, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 133304128 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 133304128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 81.otp_ctrl_stress_all_with_rand_reset.64655286576200333321749805189344349958513290888712711750237685273263821158536
      Line 29507, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19330201394 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1180 [0x49c]) dai addr 49c rdata0 readout mismatch
        UVM_INFO @ 19330201394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 92.otp_ctrl_stress_all_with_rand_reset.14335069015340417579826412886137658074506190294128613813391103258122212480963
      Line 33713, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38087424357 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38087424357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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