OTP_CTRL Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.120s	780.435us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.440s	389.878us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.500s	523.451us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.800s	864.853us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.310s	784.042us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.520s	125.061us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.500s	523.451us	20	20	100.00
		otp_ctrl_csr_aliasing	7.310s	784.042us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.160s	45.854us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.500s	517.906us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.960s	5.056ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.280s	1.839ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	33.330s	14.803ms	10	10	100.00
		otp_ctrl_check_fail	52.520s	22.601ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.090s	307.286us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	36.420s	4.440ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.060s	788.925us	50	50	100.00
		otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	57.180s	18.413ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.392m	14.596ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.046m	4.615ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.359m	191.006ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.680s	606.241us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	6.770s	372.459us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.350s	600.785us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.350s	600.785us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.440s	389.878us	5	5	100.00
		otp_ctrl_csr_rw	2.500s	523.451us	20	20	100.00
		otp_ctrl_csr_aliasing	7.310s	784.042us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.870s	1.126ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.440s	389.878us	5	5	100.00
		otp_ctrl_csr_rw	2.500s	523.451us	20	20	100.00
		otp_ctrl_csr_aliasing	7.310s	784.042us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.870s	1.126ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
		otp_ctrl_tl_intg_err	44.390s	20.229ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	44.390s	20.229ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_macro_errs	1.392m	14.596ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_macro_errs	1.392m	14.596ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.500s	19.280ms	200	200	100.00
		otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.280s	1.839ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	52.520s	22.601ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.314m	6.365ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.573m	173.514ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.090s	307.286us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.020s	1.204ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.392m	14.596ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	9.140s	3.022ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	5.899m	90.262ms	56	100	56.00
V3		TOTAL			57	101	56.44
		TOTAL			1299	1343	96.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.92	93.81	96.20	95.74	91.89	97.10	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 21 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 21 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.84434746298962516288884585615126077525435367459805403834422399700583914089761
    Line 375, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116941806 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 116941806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.32895233717062537284245384390610839630084522414259218177545100703432468653599
    Line 1495, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11347346689 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 11347346689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 12 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 12 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.104520142431015125734689246496839168273764003183495567487274769485032648951895
    Line 284, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2171586655 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4094953660 [0xf41408bc] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 2171586655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otp_ctrl_stress_all_with_rand_reset.56528228894849698199642644350153518465635076724460674390627769212053957954626
    Line 682, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1101865532 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (222113428 [0xd3d2e94] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1101865532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.53258813869947188607788697268101315257069508339171446807673661760463785064161
    Line 4444, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6989161703 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1100 [0x44c]) dai addr 44c rdata0 readout mismatch
  UVM_INFO @ 6989161703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.otp_ctrl_stress_all_with_rand_reset.70189261525930279210273515497097537998959600129057724730625123333784067245132
    Line 81, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1159009945 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 556 [0x22c]) dai addr 22c rdata0 readout mismatch
  UVM_INFO @ 1159009945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 46.otp_ctrl_stress_all_with_rand_reset.104019508156742863021478809302292392676080181616191390304531483406800156145660
    Line 5737, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 674718771 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 674718771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.otp_ctrl_stress_all_with_rand_reset.100394995549001302060876982615661121296941315827478515483760904074487255868952
    Line 3198, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2103299898 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 2103299898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=183) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.81640838628525413246396956544191918254607757666999324781419658063110092898031
    Line 59909, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14241537540 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x370bd010, Comparison=CompareOpEq, exp_data=0x0, call_count=183)
  UVM_INFO @ 14241537540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.otp_ctrl_stress_all_with_rand_reset.26987705218251131335382671778402197724643940922253780169110070055278024674733
    Line 5753, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 8811493279 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 8811493279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 67.otp_ctrl_stress_all_with_rand_reset.39050005849746304710489040814669317734529893636620621554111791838724897793084
    Line 18020, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25544393042 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25544393042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=113) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.14361048334309459922860827157593446823465592297007223909996996752035205273445
    Line 17939, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 35991963470 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xa47d8010, Comparison=CompareOpEq, exp_data=0x0, call_count=113)
  UVM_INFO @ 35991963470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 85.otp_ctrl_stress_all_with_rand_reset.103630105945157147718635003775689694217867826878109337441064034420020482050380
    Line 20045, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5419493865 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1728582276 [0x67081284]) dai addr 780 rdata0 readout mismatch
  UVM_INFO @ 5419493865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 91.otp_ctrl_stress_all_with_rand_reset.32019762060550451031750041484573824097231256800342326422019343721804721023492
    Line 8402, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2024784504 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
  UVM_INFO @ 2024784504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `34b8fc33e3`