OTP_CTRL Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.480s	776.369us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.230s	186.067us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.000s	582.688us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.940s	916.589us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.170s	3.259ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.090s	1.651ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.000s	582.688us	20	20	100.00
		otp_ctrl_csr_aliasing	9.170s	3.259ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.290s	135.103us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.450s	549.903us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	14.800s	606.032us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	6.170s	2.529ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.860s	14.211ms	10	10	100.00
		otp_ctrl_check_fail	37.330s	17.679ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.270s	4.977ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	30.000s	2.568ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.300s	12.401ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	51.610s	22.836ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	53.280s	6.857ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.446m	17.543ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.173m	34.197ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.990s	588.605us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.440s	196.011us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.840s	3.440ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.840s	3.440ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.230s	186.067us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	582.688us	20	20	100.00
		otp_ctrl_csr_aliasing	9.170s	3.259ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.830s	114.031us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.230s	186.067us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	582.688us	20	20	100.00
		otp_ctrl_csr_aliasing	9.170s	3.259ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.830s	114.031us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
		otp_ctrl_tl_intg_err	36.220s	20.020ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	36.220s	20.020ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_macro_errs	53.280s	6.857ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_macro_errs	53.280s	6.857ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	25.570s	3.009ms	200	200	100.00
		otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	6.170s	2.529ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	37.330s	17.679ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.091m	32.387ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.971m	15.176ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.270s	4.977ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.110s	2.055ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	53.280s	6.857ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.420s	5.947ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.857m	16.535ms	58	100	58.00
V3		TOTAL			59	101	58.42
		TOTAL			1301	1343	96.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.85	93.86	96.18	95.75	91.65	96.91	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 14 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 14 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.25429342351823452827479999021207352702610569764106909818266218267550249217936
    Line 14016, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7149973526 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 7149973526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_stress_all_with_rand_reset.109639633696851469617333881543366671100429087693984067962666906809754125338858
    Line 18008, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50473018482 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 50473018482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 14 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 14 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.5395761381876460087946833580483407875183962969741304410732708817074635063210
    Line 647, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3469123655 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1718560813 [0x666f282d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 3469123655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.otp_ctrl_stress_all_with_rand_reset.5304289318747789102862118033322332125136900888916531530557477158220319305304
    Line 5303, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 798089291 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3026016448 [0xb45d58c0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 798089291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.113103628660647440337751282958917801284087876213668630164882598348653061532997
    Line 5809, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2069552624 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 2069552624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otp_ctrl_stress_all_with_rand_reset.21424805275206582972271564966827099426041805872169849403505275624650598953935
    Line 155, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  51776118 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @  51776118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.106824202067259286621037490020767785555780962768804604574138242523565283834844
    Line 7410, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26315687390 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2796449824 [0xa6ae7020]) dai addr 700 rdata0 readout mismatch
  UVM_INFO @ 26315687390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.otp_ctrl_stress_all_with_rand_reset.424724698765073942970622915334254763410716345551581914816871661535013274510
    Line 4130, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4720295379 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 372 [0x174]) dai addr 174 rdata0 readout mismatch
  UVM_INFO @ 4720295379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.otp_ctrl_stress_all_with_rand_reset.16311547991850982146396749377088340917389995177475759128707377578581740330840
    Line 27274, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34809142431 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34809142431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.43656926039846281049003671646212954616787825574010873284449802208067957537113
    Line 366, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1518356914 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 1518356914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

67.otp_ctrl_stress_all_with_rand_reset.35489573422381622790871017780171469290680142928596696037869348805521708090522
Line 5508, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 3273905423 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 3274030424 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3274113758 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3275155433 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3275280434 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 82.otp_ctrl_stress_all_with_rand_reset.60868013278418770623725460787438380793102660576374725700569482280648342428383
    Line 6312, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10116059053 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1644 [0x66c]) dai addr 66c rdata0 readout mismatch
  UVM_INFO @ 10116059053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:205) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 89.otp_ctrl_stress_all_with_rand_reset.43555971863857456272735936174342264145449850617517863776769450814725996029770
    Line 21590, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44922303176 ps: (otp_ctrl_scoreboard.sv:205) [uvm_test_top.env.scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 44922303176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 94.otp_ctrl_stress_all_with_rand_reset.80600336965391039317840264667923048469433992743261788222905199755122668926333
    Line 7599, in log /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1855593297 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1855593297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```