OTP_CTRL Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.700s	142.531us	1	1	100.00
V1	smoke	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.020s	211.883us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	4.150s	625.288us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.030s	493.428us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.720s	384.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	8.320s	1.616ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	4.150s	625.288us	20	20	100.00
		otp_ctrl_csr_aliasing	8.720s	384.807us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.160s	73.178us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.170s	38.460us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	26.850s	722.144us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.670s	2.231ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	56.300s	22.155ms	10	10	100.00
		otp_ctrl_check_fail	1.201m	29.585ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.180s	4.608ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.257m	6.591ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	47.930s	9.952ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.381m	17.221ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	3.433m	31.702ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.474m	10.114ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	10.546m	27.987ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	3.370s	544.930us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	6.030s	502.355us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.820s	188.506us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.820s	188.506us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.020s	211.883us	5	5	100.00
		otp_ctrl_csr_rw	4.150s	625.288us	20	20	100.00
		otp_ctrl_csr_aliasing	8.720s	384.807us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.930s	452.361us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.020s	211.883us	5	5	100.00
		otp_ctrl_csr_rw	4.150s	625.288us	20	20	100.00
		otp_ctrl_csr_aliasing	8.720s	384.807us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.930s	452.361us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
		otp_ctrl_tl_intg_err	46.680s	19.063ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	46.680s	19.063ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_macro_errs	3.433m	31.702ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_macro_errs	3.433m	31.702ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.410s	16.425ms	200	200	100.00
		otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.670s	2.231ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.201m	29.585ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.277m	30.290ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.325m	154.964ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.180s	4.608ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	23.350s	1.196ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	3.433m	31.702ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.620s	2.992ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	5.139m	19.413ms	53	100	53.00
V3		TOTAL			54	101	53.47
		TOTAL			1296	1343	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.76	93.74	96.13	95.93	91.17	96.96	96.28	93.14

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 26 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.46541557036798992815133077938427290791617827428415729709683805626064984928762
      Line 8009, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5971937632 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 5971937632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.23658628513626355013488534695449193986573663213746341845972495037972438248278
      Line 14496, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12409644429 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 12409644429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 11 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 11 failures.

    • 17.otp_ctrl_stress_all_with_rand_reset.77832405592911366777727487358270892137517249896053089200076890141737820888292
      Line 3839, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15489867672 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3324123421 [0xc622191d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 15489867672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.otp_ctrl_stress_all_with_rand_reset.77982132438959405902413395993287360465680270764640583353867048642635329280896
      Line 24356, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1354196421 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (614012295 [0x24991587] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1354196421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 29.otp_ctrl_stress_all_with_rand_reset.13001371701162873106207301518524914522495180055041179847722209513474141516499
      Line 4747, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 127324810 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 127324810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.otp_ctrl_stress_all_with_rand_reset.39453443336738663197841256386466510128003305526642178722271179366568464696212
      Line 32098, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63263352959 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 63263352959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.97226431007919081348277154109765445383415396554826865278190724383386411115340
      Line 18653, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27890626107 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27890626107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 55.otp_ctrl_stress_all_with_rand_reset.39066130264177064556329666461829486350737873105593618990906151656216327966905
      Line 2844, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3561635205 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3561635205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.88706578335255653589898678164282930817356287494581838857324853348923296509086
      Line 82, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  29702935 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  29702935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 20.otp_ctrl_stress_all_with_rand_reset.23577254055310697747239513786307730890428992924134052207293030233733258796242
      Line 193, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 258977552 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 258977552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ec rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.65014412212995513119969922859268246133540353789842546965451694502074672132081
      Line 82, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2773741215 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1260 [0x4ec]) dai addr 4ec rdata0 readout mismatch
        UVM_INFO @ 2773741215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *cc rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 95.otp_ctrl_stress_all_with_rand_reset.20685342860997978113185350443940058345611566093545517933522687410496122455419
      Line 745, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4322941011 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 460 [0x1cc]) dai addr 1cc rdata0 readout mismatch
        UVM_INFO @ 4322941011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 97.otp_ctrl_stress_all_with_rand_reset.15240529075300052356517158746713114065055326167524083329387753207165374514341
      Line 11586, in log /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3663740240 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 3663740240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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