OTP_CTRL Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.530s	199.087us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.410s	403.260us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.090s	630.298us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.240s	6.778ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.770s	165.417us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.190s	112.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.090s	630.298us	20	20	100.00
		otp_ctrl_csr_aliasing	5.770s	165.417us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.300s	513.385us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.490s	135.684us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	13.640s	610.274us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.510s	2.480ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	25.240s	2.044ms	10	10	100.00
		otp_ctrl_check_fail	53.900s	4.941ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.500s	5.189ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.570s	20.591ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.480s	12.988ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	44.900s	3.124ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	3.046m	18.523ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.001m	12.031ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.559m	145.427ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.140s	552.159us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.240s	288.415us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.670s	3.234ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.670s	3.234ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.410s	403.260us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	630.298us	20	20	100.00
		otp_ctrl_csr_aliasing	5.770s	165.417us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.070s	1.697ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.410s	403.260us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	630.298us	20	20	100.00
		otp_ctrl_csr_aliasing	5.770s	165.417us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.070s	1.697ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.590s	20.107ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.590s	20.107ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_macro_errs	3.046m	18.523ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_macro_errs	3.046m	18.523ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.910s	15.653ms	200	200	100.00
		otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.510s	2.480ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.900s	4.941ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	45.670s	13.027ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.236m	15.323ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.500s	5.189ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.830s	6.368ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	3.046m	18.523ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	9.590s	7.336ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.895m	10.104ms	65	100	65.00
V3		TOTAL			66	101	65.35
		TOTAL			1308	1343	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.81	96.18	95.63	92.36	97.10	96.34	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 16 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 16 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.65246664594810173427287145577311289626065389238721403250495470533443429475528
      Line 12769, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5453549399 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 5453549399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.otp_ctrl_stress_all_with_rand_reset.17800594427631139803854692998879302221011602786450239924218375995907340381089
      Line 2024, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8021925508 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 8021925508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 9 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.107935136964117999258494894534494435017382558559769602808457883713617259816794
      Line 3891, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 916786950 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (645618262 [0x267b5a56] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 916786950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.otp_ctrl_stress_all_with_rand_reset.61332465187364912865623309940448235889428568437623431630088996658175708043958
      Line 15024, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17032785699 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2172098421 [0x81779775] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 17032785699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 20.otp_ctrl_stress_all_with_rand_reset.59550289353221727655482765434739231708866353303197107788502848037123970887344
      Line 1021, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2388990472 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 2388990472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 55.otp_ctrl_stress_all_with_rand_reset.65032964615684729459990686072934012085708932490269064195562068668227084755008
      Line 21261, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4422079316 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 4422079316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 47.otp_ctrl_stress_all_with_rand_reset.21664636572620174025867136755846038368281839240462085524790192484611433679214
      Line 87584, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24713550411 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24713550411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 82.otp_ctrl_stress_all_with_rand_reset.69130407254985650805744065722245899177949942111280703706058294079327524767585
      Line 19454, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19780758206 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19780758206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.69941319186352690294384788934192849960417366450555793996506134575247463007576
      Line 14653, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 6323224915 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 6323224915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 56.otp_ctrl_stress_all_with_rand_reset.63426179432455937256033751900385824711169345733329309881770975856693443036695
      Line 4929, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29917967168 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 680 [0x2a8]) dai addr 2a8 rdata0 readout mismatch
        UVM_INFO @ 29917967168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=292) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 92.otp_ctrl_stress_all_with_rand_reset.10035119813919635738820979661237785726872366567978414370925979530761087078591
      Line 33243, in log /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 33736950969 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xa9fd7010, Comparison=CompareOpEq, exp_data=0x0, call_count=292)
        UVM_INFO @ 33736950969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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