OTP_CTRL Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.700s	63.495us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.400s	1.557ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.510s	68.670us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.090s	6.864ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.540s	2.985ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.080s	989.554us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.510s	68.670us	20	20	100.00
		otp_ctrl_csr_aliasing	7.540s	2.985ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.210s	37.048us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.080s	131.338us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	28.250s	654.871us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	14.120s	3.222ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.063m	26.201ms	10	10	100.00
		otp_ctrl_check_fail	1.517m	14.463ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.670s	3.822ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.786m	20.610ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	41.800s	9.568ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.370m	22.769ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.049m	5.286ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.363m	31.548ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	13.462m	66.552ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.550s	598.229us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	7.470s	410.325us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.990s	303.610us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.990s	303.610us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.400s	1.557ms	5	5	100.00
		otp_ctrl_csr_rw	2.510s	68.670us	20	20	100.00
		otp_ctrl_csr_aliasing	7.540s	2.985ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.600s	266.100us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.400s	1.557ms	5	5	100.00
		otp_ctrl_csr_rw	2.510s	68.670us	20	20	100.00
		otp_ctrl_csr_aliasing	7.540s	2.985ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.600s	266.100us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.200s	4.968ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.200s	4.968ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_macro_errs	1.049m	5.286ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_macro_errs	1.049m	5.286ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.023m	14.105ms	200	200	100.00
		otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	14.120s	3.222ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.517m	14.463ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.195m	24.292ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.244m	12.397ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.670s	3.822ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.050s	1.587ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.049m	5.286ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	25.860s	6.891ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.704m	73.576ms	52	100	52.00
V3		TOTAL			53	101	52.48
		TOTAL			1293	1343	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.70	93.76	96.20	95.67	90.69	97.00	96.28	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 30 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 30 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.101104445011158605491199833740152102604492415930325646681018249036801021124056
      Line 14502, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5593040163 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 5593040163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.otp_ctrl_stress_all_with_rand_reset.20994810196308799668276726687689128690670516862012447940301570000970717598224
      Line 147, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  40498132 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @  40498132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 15 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 15 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.15319222995869962091728369693265629936786784631707480540979129591262195086116
      Line 1427, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 235112344 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (797815350 [0x2f8db236] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 235112344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.otp_ctrl_stress_all_with_rand_reset.76618587699084745743632321583111072418075159347633860877663598454572620369869
      Line 369, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112538037 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1330606844 [0x4f4f72fc] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 112538037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.

    • 5.otp_ctrl_csr_mem_rw_with_rand_reset.60622278235263827196797612023964233627520110298129573070944236182940025682647
      Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 989553849 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 989553849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 6.otp_ctrl_csr_mem_rw_with_rand_reset.7609197265622579578725631530553161682060109959649720793855542863289044112339
      Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 249499428 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 249499428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.otp_ctrl_stress_all_with_rand_reset.52658590848395451884150000912513550092916711100881187935460129161499911679015
      Line 19190, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7958040266 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1148 [0x47c]) dai addr 47c rdata0 readout mismatch
        UVM_INFO @ 7958040266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.43590478898300084202423676369526588785025658355383823079893279336699932230308
      Line 16574, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21950720969 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
        UVM_INFO @ 21950720969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.otp_ctrl_stress_all_with_rand_reset.30962715769627795348644109290351563454723270706455167628902269736309255628331
      Line 1840, in log /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 490802656 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 490802656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.28_06.56.55
• 2024.08.26_02.18.19
• 2024.08.24_20.10.06
• 2024.08.22_14.11.39
• 2024.08.20_07.55.11
• 2024.08.19_08.08.52