OTP_CTRL Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	3.240s	782.687us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.730s	264.207us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.830s	559.505us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.820s	392.023us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.660s	304.644us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.230s	107.445us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.830s	559.505us	20	20	100.00
		otp_ctrl_csr_aliasing	9.660s	304.644us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.260s	131.479us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.260s	74.024us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	26.330s	709.782us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.920s	2.398ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.367m	27.813ms	10	10	100.00
		otp_ctrl_check_fail	1.079m	9.128ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	22.540s	5.290ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.383m	19.607ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	56.580s	10.976ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	56.880s	1.646ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.405m	11.110ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.178m	6.695ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	31.413m	150.733ms	48	50	96.00
V2	intr_test	otp_ctrl_intr_test	3.020s	568.184us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.730s	197.830us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	11.660s	378.142us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	11.660s	378.142us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.730s	264.207us	5	5	100.00
		otp_ctrl_csr_rw	2.830s	559.505us	20	20	100.00
		otp_ctrl_csr_aliasing	9.660s	304.644us	5	5	100.00
		otp_ctrl_same_csr_outstanding	9.870s	1.794ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.730s	264.207us	5	5	100.00
		otp_ctrl_csr_rw	2.830s	559.505us	20	20	100.00
		otp_ctrl_csr_aliasing	9.660s	304.644us	5	5	100.00
		otp_ctrl_same_csr_outstanding	9.870s	1.794ms	20	20	100.00
V2		TOTAL			1099	1101	99.82
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
		otp_ctrl_tl_intg_err	1.058m	19.863ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	1.058m	19.863ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_macro_errs	1.405m	11.110ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_macro_errs	1.405m	11.110ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.001m	17.160ms	200	200	100.00
		otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.920s	2.398ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.079m	9.128ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	3.316m	21.443ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.502m	154.565ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	22.540s	5.290ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.440s	6.589ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.405m	11.110ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	21.660s	5.924ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.305m	14.858ms	56	100	56.00
V3		TOTAL			57	101	56.44
		TOTAL			1296	1343	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.78	93.81	96.18	95.85	90.93	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 17 failures:

Test otp_ctrl_stress_all has 1 failures.

0.otp_ctrl_stress_all.38167546676007000367638449132921614328771655689923643574825854098222959533176
Line 70955, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10885473590 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2779409841 [0xa5aa6db1] vs 4025154995 [0xefeafdb3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 10885473590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otp_ctrl_stress_all_with_rand_reset has 16 failures.

7.otp_ctrl_stress_all_with_rand_reset.92715989001951872876672095379808736986094838664902865595824737535981447515707
Line 20487, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14972604883 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2114446508 [0x7e07e4ac] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 14972604883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.otp_ctrl_stress_all_with_rand_reset.71862535460796082085773939772961955418485114292421488193322722487087372080832
Line 531, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 176004542 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3339673053 [0xc70f5ddd] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 176004542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 17 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 3.otp_ctrl_stress_all.32320517143452788500622156360448881017042437094433750178509946253513908878076
    Line 33842, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7317393151 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 7317393151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 16 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.45081171378582211871932721102854518571540651941448874220660707060433226821557
    Line 11401, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32037719732 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 32037719732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otp_ctrl_stress_all_with_rand_reset.41833332002665177915574900865405465263963879948966461428637254956365507640355
    Line 12618, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 952578736 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 952578736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.otp_ctrl_csr_mem_rw_with_rand_reset.25644654109440458500739717890444397907948450330376982750254429778772212727120
    Line 80, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 427961055 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 427961055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.84674048584231418994288844058620266517885211233750319528166418926502017089418
    Line 3232, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 748232530 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 748232530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 81.otp_ctrl_stress_all_with_rand_reset.5841810374285794528260370670566729281340937734751856637787848760126953897106
    Line 1640, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 191803159 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 191803159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.78908951539093391410058720527103782483008135981621625481239390834769301417502
    Line 17421, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42455533655 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 42455533655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 91.otp_ctrl_stress_all_with_rand_reset.57395070311702999647794782004827325168149340486273117607052464561086891828097
    Line 12992, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5410502128 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 5410502128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 21.otp_ctrl_stress_all_with_rand_reset.12908076534941035477745974267295221057824962301780328956975776628866412297314
    Line 10732, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8772960250 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8772960250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 84.otp_ctrl_stress_all_with_rand_reset.113662323657698678482413265400598436223775886832904949122987805660651290153187
    Line 47418, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32925977683 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32925977683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 43.otp_ctrl_stress_all_with_rand_reset.103739250991671660275328507564270227698161408203505967277339797679384429556311
    Line 8323, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11775241454 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 140 [0x8c]) dai addr 8c rdata0 readout mismatch
  UVM_INFO @ 11775241454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.otp_ctrl_stress_all_with_rand_reset.37901978437101691222005305217077302236767272444689218920544740995704243172599
    Line 82, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1950380342 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 892 [0x37c]) dai addr 37c rdata0 readout mismatch
  UVM_INFO @ 1950380342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

41.otp_ctrl_stress_all_with_rand_reset.46511146027693734671221290069376715506034860389977805446086658904909556764675
Line 17728, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 32212916080 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 32213416081 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 32216416087 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 32217916090 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 32221749431 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=255) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 50.otp_ctrl_stress_all_with_rand_reset.66124968355319267827564148204238563511415723159292206612564858510060904221460
    Line 32945, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 34968575771 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x654b1010, Comparison=CompareOpEq, exp_data=0x0, call_count=255)
  UVM_INFO @ 34968575771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 85.otp_ctrl_stress_all_with_rand_reset.6897415145495240588840275245373060346354991562048354530119473754278200967203
    Line 16328, in log /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32878808412 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1232 [0x4d0]) dai addr 4d0 rdata0 readout mismatch
  UVM_INFO @ 32878808412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```