OTP_CTRL Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.260s	220.595us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.530s	1.017ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	3.290s	653.222us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.670s	1.672ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.980s	2.986ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.070s	204.316us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	3.290s	653.222us	20	20	100.00
		otp_ctrl_csr_aliasing	8.980s	2.986ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.280s	68.119us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.310s	72.610us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.420s	1.603ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.130s	2.271ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.242m	7.050ms	10	10	100.00
		otp_ctrl_check_fail	1.718m	65.314ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.830s	4.661ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.130s	4.322ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.180s	10.691ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2	otp_dai_errors	otp_ctrl_dai_errs	48.970s	21.233ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.192m	30.246ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	45.870s	4.686ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.048m	140.171ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.690s	554.885us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.450s	324.389us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.410s	3.216ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.410s	3.216ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.530s	1.017ms	5	5	100.00
		otp_ctrl_csr_rw	3.290s	653.222us	20	20	100.00
		otp_ctrl_csr_aliasing	8.980s	2.986ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.410s	426.248us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.530s	1.017ms	5	5	100.00
		otp_ctrl_csr_rw	3.290s	653.222us	20	20	100.00
		otp_ctrl_csr_aliasing	8.980s	2.986ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.410s	426.248us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
		otp_ctrl_tl_intg_err	45.710s	20.004ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	45.710s	20.004ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_macro_errs	1.192m	30.246ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_macro_errs	1.192m	30.246ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.350s	19.503ms	199	200	99.50
		otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.130s	2.271ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.718m	65.314ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.401m	28.317ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.290m	165.661ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.830s	4.661ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.830s	379.053us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.192m	30.246ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.410s	5.923ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.886m	97.749ms	58	100	58.00
V3		TOTAL			59	101	58.42
		TOTAL			1299	1343	96.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.69	96.60	95.68	91.57	97.47	96.34	93.14

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 21 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.83210513872602483859697072890131837668221733872620196372316092645589306915369
      Line 14727, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33172195998 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 33172195998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.otp_ctrl_stress_all_with_rand_reset.102879707097690235015165390488043807103395284620764045938217436183306003859146
      Line 71366, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2748900568 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 2748900568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 14 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 14 failures.

    • 3.otp_ctrl_stress_all_with_rand_reset.45672113339674476054608371471511224985723530900564006009652096931519290187701
      Line 19654, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2575406401 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3558268463 [0xd416de2f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 2575406401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.otp_ctrl_stress_all_with_rand_reset.110801361745070591377469678056015528287356952221710906162044296601388171997400
      Line 1830, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 190846402 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1762247032 [0x6909c178] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 190846402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 33.otp_ctrl_stress_all_with_rand_reset.113309559394017516540260111170395110929523713090034783970807571074059687836363
      Line 248, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 358661978 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 358661978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.otp_ctrl_stress_all_with_rand_reset.4677882265943381456843814033299917370690678397735332379983248395661051231727
      Line 12590, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16081213728 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 16081213728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 55.otp_ctrl_stress_all_with_rand_reset.44327700558643454796605164852475915066111968337725956729393549736112212820931
      Line 3381, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3385096558 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1307263554 [0x4deb4242]) dai addr 724 rdata0 readout mismatch
        UVM_INFO @ 3385096558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 80.otp_ctrl_stress_all_with_rand_reset.823072937270382567514213996838465985523418973151007110764517668212190763052
      Line 82, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3562589307 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1169925309 [0x45bba4bd]) dai addr 790 rdata0 readout mismatch
        UVM_INFO @ 3562589307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 9.otp_ctrl_csr_mem_rw_with_rand_reset.97468824028138270664281636761226280327045511664951507658851859454736407616970
      Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 116715608 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 116715608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *e* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 99.otp_ctrl_stress_all_with_rand_reset.30519771406859170801167703599774992187482449192044721857468732925618255231984
      Line 238, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17176775772 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1715401312 [0x663ef260]) dai addr 6e0 rdata0 readout mismatch
        UVM_INFO @ 17176775772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:

  • Test otp_ctrl_parallel_lc_esc has 1 failures.

    • 159.otp_ctrl_parallel_lc_esc.110113716137168184793011835809937569033814744435226774744587990494807491680598
      Line 2729, in log /workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest/run.log

        UVM_ERROR @ 177447462 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
        UVM_INFO @ 177447462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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