OTP_CTRL Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.650s	61.249us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.460s	195.366us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.470s	42.108us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.730s	473.316us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.470s	166.154us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.970s	1.680ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.470s	42.108us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	166.154us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.440s	508.052us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.650s	65.730us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.950s	768.878us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.460s	2.553ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	28.770s	3.372ms	10	10	100.00
		otp_ctrl_check_fail	47.220s	25.189ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.950s	4.685ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	57.740s	29.312ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.790s	1.044ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.650s	18.882ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	58.880s	31.717ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	47.560s	28.796ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	4.085m	22.451ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.510s	582.361us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.670s	233.940us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.430s	380.273us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.430s	380.273us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.460s	195.366us	5	5	100.00
		otp_ctrl_csr_rw	2.470s	42.108us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	166.154us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	372.721us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.460s	195.366us	5	5	100.00
		otp_ctrl_csr_rw	2.470s	42.108us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	166.154us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	372.721us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
		otp_ctrl_tl_intg_err	1.044m	20.009ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	1.044m	20.009ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_macro_errs	58.880s	31.717ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_macro_errs	58.880s	31.717ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.190s	16.931ms	200	200	100.00
		otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.460s	2.553ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.220s	25.189ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	52.160s	3.913ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.233m	12.057ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.950s	4.685ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.090s	1.640ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	58.880s	31.717ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.200s	3.454ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.424m	62.474ms	55	100	55.00
V3		TOTAL			56	101	55.45
		TOTAL			1297	1343	96.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.03	93.71	97.25	96.08	91.08	97.66	96.34	93.07

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 19 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 19 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.93896201427740767995614238409100444096369221594091325946523367746743990613046
    Line 36052, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6353594125 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (89800240 [0x55a3e30] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 6353594125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.otp_ctrl_stress_all_with_rand_reset.111723953274034885765090892266459095164072243602713125029192640141806230151826
    Line 14263, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 240135449 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3295181651 [0xc4687b53] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 240135449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 19 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 19 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.60665073942476930987056628559949709688504902685972622685121807258619872455003
    Line 8314, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18499722319 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 18499722319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_stress_all_with_rand_reset.52267817704286939301002595969796246445614908516738729421778521883900547472336
    Line 212, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  77025993 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  77025993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.otp_ctrl_csr_mem_rw_with_rand_reset.3671802805009378773389822573729194665450762801265028440119789675483630245673
    Line 80, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  67328779 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  67328779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.otp_ctrl_stress_all_with_rand_reset.86818878633001564458060189176538030739534292858585777835621118454796847603472
    Line 271, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1093025133 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1093025133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.68366215140238976490387629630509527264855930172910196172425959296532032632575
    Line 20576, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19575869170 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19575869170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.otp_ctrl_stress_all_with_rand_reset.1943162306032287535927026661926960312483133595032634215335523882916275180614
    Line 19594, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29466942733 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29466942733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 74.otp_ctrl_stress_all_with_rand_reset.49077684357714455480474514241911623095224345488736972591348589609240175949599
    Line 53335, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10001599118 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1336 [0x538]) dai addr 538 rdata0 readout mismatch
  UVM_INFO @ 10001599118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 85.otp_ctrl_stress_all_with_rand_reset.106844326670071342584444143816772524996309048546313458972621088730880407546585
    Line 5088, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27865994345 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 457722354 [0x1b4849f2]) dai addr 750 rdata0 readout mismatch
  UVM_INFO @ 27865994345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=121) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.110615912758067088829482162352356014893542660493615670035600521649967420544190
    Line 22335, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22003136227 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x1767d010, Comparison=CompareOpEq, exp_data=0x0, call_count=121)
  UVM_INFO @ 22003136227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *e* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.otp_ctrl_stress_all_with_rand_reset.34286180004618316207636305652587233389946349132181012364045017281941186023226
    Line 1129, in log /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4730834350 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 322842446 [0x133e2f4e]) dai addr 6e4 rdata0 readout mismatch
  UVM_INFO @ 4730834350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`