OTP_CTRL Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.720s	92.677us	1	1	100.00
V1	smoke	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	7.770s	1.595ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.800s	604.405us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	14.520s	5.615ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.470s	377.925us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.750s	338.819us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.800s	604.405us	20	20	100.00
		otp_ctrl_csr_aliasing	7.470s	377.925us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.320s	71.402us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.240s	71.795us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.550s	1.575ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.560s	2.589ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	34.760s	5.069ms	10	10	100.00
		otp_ctrl_check_fail	37.570s	3.017ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.670s	388.472us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.750s	15.052ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	43.470s	12.099ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	45.180s	1.837ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	58.560s	8.855ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	45.030s	13.821ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.885m	37.231ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.680s	592.414us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.490s	548.082us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.520s	172.664us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.520s	172.664us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	7.770s	1.595ms	5	5	100.00
		otp_ctrl_csr_rw	2.800s	604.405us	20	20	100.00
		otp_ctrl_csr_aliasing	7.470s	377.925us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.500s	1.908ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	7.770s	1.595ms	5	5	100.00
		otp_ctrl_csr_rw	2.800s	604.405us	20	20	100.00
		otp_ctrl_csr_aliasing	7.470s	377.925us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.500s	1.908ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.350s	19.851ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.350s	19.851ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_macro_errs	58.560s	8.855ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_macro_errs	58.560s	8.855ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.800s	11.827ms	200	200	100.00
		otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.560s	2.589ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	37.570s	3.017ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	43.780s	5.587ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.392m	154.676ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.670s	388.472us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	23.350s	4.897ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	58.560s	8.855ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.860s	6.883ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.554m	72.114ms	48	100	48.00
V3		TOTAL			49	101	48.51
		TOTAL			1291	1343	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.71	96.70	95.53	91.81	97.51	96.34	93.07

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 29 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 29 failures.

    • 8.otp_ctrl_stress_all_with_rand_reset.46014563521520179981735867727271662544398948945872627607257516110824583390548
      Line 21126, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2789999567 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 2789999567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.otp_ctrl_stress_all_with_rand_reset.104107482934610199777033936181091724279377475408915241217321731842100235318649
      Line 15038, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25868265628 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 25868265628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 18 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 18 failures.

    • 11.otp_ctrl_stress_all_with_rand_reset.99979345621756424157795930507157236734943837723079281736382142108960115715482
      Line 3612, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1267179297 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3520006460 [0xd1cf093c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1267179297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.otp_ctrl_stress_all_with_rand_reset.45774984693726858447853902509553166985620804462453059529139961002143674202677
      Line 176, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1133310619 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2893673324 [0xac79f36c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1133310619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *a348e*, csr_addr * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.otp_ctrl_stress_all_with_rand_reset.105335301582384133182476655569747234384794546366978200172105213949806320265671
      Line 8669, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1438565760 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (4160674710 [0xf7fedb96] vs 3543194248 [0xd330da88]) mem read mismatch at TLUL addr 5a348e70, csr_addr 670
        UVM_INFO @ 1438565760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 53.otp_ctrl_stress_all_with_rand_reset.99399657628112888657859967205385180769905103924207241020481734507918054350832
      Line 39765, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10080784684 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 10080784684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 61.otp_ctrl_stress_all_with_rand_reset.109793780142523625078020906500444072566333662566343133375998747665112197396233
      Line 82, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3178428822 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1704 [0x6a8]) dai addr 6a8 rdata0 readout mismatch
        UVM_INFO @ 3178428822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 76.otp_ctrl_stress_all_with_rand_reset.11723788811781321508781172955049692841013289681894272142575602489633394769053
      Line 29780, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11721097685 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1052 [0x41c]) dai addr 41c rdata0 readout mismatch
        UVM_INFO @ 11721097685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 99.otp_ctrl_stress_all_with_rand_reset.111641357837189094311738320382886181728806025845160510441738607397596848128991
      Line 12477, in log /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 514626871 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 514626871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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