042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 6.000s | 328.849us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 7.000s | 42.737us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 7.000s | 20.484us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 9.000s | 1.141ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 7.000s | 96.670us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 3.000s | 30.174us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 7.000s | 20.484us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 7.000s | 96.670us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.633m | 3.990ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.783m | 5.595ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 6.000s | 102.191us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.800m | 4.130ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 8.000s | 21.763us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 7.000s | 14.037us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 9.000s | 99.473us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 9.000s | 99.473us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 7.000s | 42.737us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 20.484us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 96.670us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 10.000s | 20.911us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 7.000s | 42.737us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 20.484us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 96.670us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 10.000s | 20.911us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 12.000s | 88.426us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 62.271us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 12.000s | 88.426us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 36.283m | 110.715ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 515 | 520 | 99.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
3.pattgen_stress_all_with_rand_reset.50111048699173202637568926338456628670139306794783700322948152816215908244590
Line 887, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90840464274 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
7.pattgen_stress_all_with_rand_reset.67361193138702131379367097793440993401830360275093616394762214021129044326393
Line 578, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19139105894 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 3 more failures.