cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 12.000s | 215.489us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 14.287us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 71.399us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 282.797us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 31.499us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 8.000s | 41.713us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 71.399us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 31.499us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.850m | 15.786ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.833m | 13.845ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 22.616us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 3.650m | 23.313ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 6.000s | 25.519us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 8.000s | 18.893us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 41.681us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 41.681us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 14.287us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 71.399us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 31.499us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 55.095us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 14.287us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 71.399us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 31.499us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 55.095us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 7.000s | 505.503us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 77.653us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 7.000s | 505.503us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 32.733m | 196.886ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 515 | 520 | 99.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
4.pattgen_stress_all_with_rand_reset.68937814207522216281650382667668677853830269604497976344438417261725308040809
Line 345, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 980924753 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
15.pattgen_stress_all_with_rand_reset.94842744623675565351935260349999939056131239858742280815682357432698345531518
Line 309, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 567430673 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 3 more failures.