5f48fbc0e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 21.000s | 382.091us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 4.000s | 26.603us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 4.000s | 13.100us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 86.972us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 7.000s | 33.706us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 17.000s | 39.154us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 4.000s | 13.100us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 7.000s | 33.706us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.683m | 4.070ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.850m | 16.433ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 3.000s | 40.892us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.700m | 15.998ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 7.000s | 74.016us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 7.000s | 13.590us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 13.000s | 27.136us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 13.000s | 27.136us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 4.000s | 26.603us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 13.100us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 33.706us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 12.000s | 76.443us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 4.000s | 26.603us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 13.100us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 33.706us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 12.000s | 76.443us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 8.000s | 76.036us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 7.000s | 120.521us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 8.000s | 76.036us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 33.883m | 85.420ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 514 | 520 | 98.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
4.pattgen_stress_all_with_rand_reset.79490233333739300804831195870158152891246894540099983029790152645225137757338
Line 396, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7206281626 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
9.pattgen_stress_all_with_rand_reset.73302405802414865228096929983053979126165917859347977463139946538437319154286
Line 453, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14939299148 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.