PATTGEN Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	613.614us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	95.956us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	15.432us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	194.002us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	30.104us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	31.609us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	15.432us	20	20	100.00
		pattgen_csr_aliasing	7.000s	30.104us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	2.746ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	2.635ms	50	50	100.00
V2	error	pattgen_error	7.000s	37.575us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.767m	13.387ms	50	50	100.00
V2	alert_test	pattgen_alert_test	4.000s	32.468us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	18.309us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	158.491us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	158.491us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	95.956us	5	5	100.00
		pattgen_csr_rw	4.000s	15.432us	20	20	100.00
		pattgen_csr_aliasing	7.000s	30.104us	5	5	100.00
		pattgen_same_csr_outstanding	9.000s	25.363us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	95.956us	5	5	100.00
		pattgen_csr_rw	4.000s	15.432us	20	20	100.00
		pattgen_csr_aliasing	7.000s	30.104us	5	5	100.00
		pattgen_same_csr_outstanding	9.000s	25.363us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	775.234us	20	20	100.00
		pattgen_sec_cm	3.000s	78.202us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	775.234us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.167m	118.484ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 29 failures:

Test pattgen_stress_all_with_rand_reset has 29 failures.

0.pattgen_stress_all_with_rand_reset.66328795104777900950177772616847377024644845439119307152953097380243837864618
Line 300, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3941432795 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3941443730 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3941443730 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 3941586588 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.25728078377445782599222094979777137954525541208022908302440975558044070191231
Line 331, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2636543888 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2636564528 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2636564528 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 2636840392 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 27 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 2.pattgen_stress_all_with_rand_reset.101522207099998589140548614213487852839165258408010001728152915838676564532978
    Line 885, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 300280883286 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 10.pattgen_stress_all_with_rand_reset.27059905904197187280147324856460642266433623612440389487693904637887238751225
    Line 496, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8484776363 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.