PATTGEN Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	116.012us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	40.528us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	41.858us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	568.988us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	51.288us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	31.072us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	41.858us	20	20	100.00
		pattgen_csr_aliasing	4.000s	51.288us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.850m	15.786ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	10.009ms	50	50	100.00
V2	error	pattgen_error	8.000s	20.528us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.650m	6.906ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	15.537us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	20.729us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	7.000s	345.197us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	7.000s	345.197us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	40.528us	5	5	100.00
		pattgen_csr_rw	4.000s	41.858us	20	20	100.00
		pattgen_csr_aliasing	4.000s	51.288us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	181.225us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	40.528us	5	5	100.00
		pattgen_csr_rw	4.000s	41.858us	20	20	100.00
		pattgen_csr_aliasing	4.000s	51.288us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	181.225us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	62.671us	20	20	100.00
		pattgen_sec_cm	3.000s	1.032ms	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	62.671us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.383m	196.221ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			479	520	92.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 35 failures:

Test pattgen_stress_all_with_rand_reset has 35 failures.

3.pattgen_stress_all_with_rand_reset.110572696505634739868863224622015644402226339468271149097573463636468387814696
Line 552, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13025314657 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13025324267 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13025324267 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 13025428437 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.80123003263298997550021023795183593985963052850183118206976797517044798664153
Line 487, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9188209768 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9188214778 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9188214778 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 9188318948 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 33 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 2.pattgen_stress_all_with_rand_reset.21685927141926162368332925997367014908159987983106201330467102673926918049956
    Line 404, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9765316955 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 11.pattgen_stress_all_with_rand_reset.1746839261518288852603153061156646157746566108873032505784076715773150984739
    Line 950, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 188207337586 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.