PATTGEN Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	318.108us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	54.222us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	46.256us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.152ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	17.505us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	37.311us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	46.256us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.505us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.050m	5.375ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	10.929ms	50	50	100.00
V2	error	pattgen_error	9.000s	102.006us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.133m	2.900ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	11.406us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	66.741us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	282.581us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	282.581us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	54.222us	5	5	100.00
		pattgen_csr_rw	5.000s	46.256us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.505us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	18.346us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	54.222us	5	5	100.00
		pattgen_csr_rw	5.000s	46.256us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.505us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	18.346us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	99.740us	20	20	100.00
		pattgen_sec_cm	6.000s	111.916us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	99.740us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.683m	260.547ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 26 failures:

Test pattgen_stress_all_with_rand_reset has 26 failures.

0.pattgen_stress_all_with_rand_reset.50822194130687613837033221239359294964595053229791085855080917637353352938041
Line 352, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1651702324 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1651711584 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1651711584 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 1651742511 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.67588327041253317253019942439054689535525798524618661607425011746782545376575
Line 1241, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 70899109690 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 70899111627 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 70899111627 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 9/10
  UVM_INFO @ 70899201627 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 24 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 8 failures:
- Test pattgen_stress_all_with_rand_reset has 8 failures.
  - 4.pattgen_stress_all_with_rand_reset.98236077304542639667441543065532587499785539216971896824966205882858209540324
    Line 564, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17906017391 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 5.pattgen_stress_all_with_rand_reset.61288779916711129327396727015494069912135969880009152781379147331942833983762
    Line 374, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3031038774 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 6 more failures.