PATTGEN Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	149.850us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	8.000s	22.161us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	8.000s	11.709us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	241.284us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	122.542us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	28.767us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	8.000s	11.709us	20	20	100.00
		pattgen_csr_aliasing	5.000s	122.542us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	2.638ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	5.262ms	50	50	100.00
V2	error	pattgen_error	4.000s	21.658us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.850m	2.748ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	43.469us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	13.992us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	813.252us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	813.252us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	8.000s	22.161us	5	5	100.00
		pattgen_csr_rw	8.000s	11.709us	20	20	100.00
		pattgen_csr_aliasing	5.000s	122.542us	5	5	100.00
		pattgen_same_csr_outstanding	5.000s	88.546us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	8.000s	22.161us	5	5	100.00
		pattgen_csr_rw	8.000s	11.709us	20	20	100.00
		pattgen_csr_aliasing	5.000s	122.542us	5	5	100.00
		pattgen_same_csr_outstanding	5.000s	88.546us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	100.936us	20	20	100.00
		pattgen_sec_cm	4.000s	36.315us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	100.936us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	29.383m	218.909ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			480	520	92.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

0.pattgen_stress_all_with_rand_reset.10531480965612063193904619238860367539907813951821332433838455502509116716967
Line 887, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 108230953263 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 108230963960 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 108230963960 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 108231297296 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.102605802588498130887135917438602769636604340128080341907635561727271453157390
Line 676, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17787125580 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 17787126210 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17787126210 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 17787232590 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 22.pattgen_stress_all_with_rand_reset.82625454380526824200213100541422043112363946861366787292589272604968250298415
    Line 347, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4648933650 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 27.pattgen_stress_all_with_rand_reset.71466960504790674030797276257939259892859129649456401560852769304663203713160
    Line 746, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38978772125 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.