PATTGEN Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	15.000s	170.247us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	8.000s	21.187us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	17.065us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	489.277us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	52.047us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	62.819us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	17.065us	20	20	100.00
		pattgen_csr_aliasing	3.000s	52.047us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.783m	8.050ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.742ms	50	50	100.00
V2	error	pattgen_error	14.000s	46.718us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.933m	2.750ms	50	50	100.00
V2	alert_test	pattgen_alert_test	14.000s	11.300us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	15.844us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	25.382us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	25.382us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	8.000s	21.187us	5	5	100.00
		pattgen_csr_rw	3.000s	17.065us	20	20	100.00
		pattgen_csr_aliasing	3.000s	52.047us	5	5	100.00
		pattgen_same_csr_outstanding	10.000s	115.997us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	8.000s	21.187us	5	5	100.00
		pattgen_csr_rw	3.000s	17.065us	20	20	100.00
		pattgen_csr_aliasing	3.000s	52.047us	5	5	100.00
		pattgen_same_csr_outstanding	10.000s	115.997us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	87.604us	20	20	100.00
		pattgen_sec_cm	8.000s	39.952us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	87.604us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.983m	383.876ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.108153406475754867667093059632761300190631241971805491862441227872324507190899
Line 325, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5033191046 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5033193019 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5033193019 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 5033253019 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.42150189507129070464589110715684104289454599272795615614330721467964186904572
Line 741, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36812416329 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36812421568 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36812421568 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 36812511315 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 6.pattgen_stress_all_with_rand_reset.18489019655510767183870503058676893727367042116110653102408567487498396352456
    Line 314, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 307152176 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 17.pattgen_stress_all_with_rand_reset.50296199401175608166165352272586906393339857517210507243337342926996724128121
    Line 432, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14188215128 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.