PATTGEN Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	90.253us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	17.907us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	13.642us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	65.035us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	94.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	23.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	13.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	94.194us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.850m	15.778ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	5.330ms	50	50	100.00
V2	error	pattgen_error	3.000s	107.997us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.533m	46.830ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	14.802us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	34.446us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	619.640us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	619.640us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	17.907us	5	5	100.00
		pattgen_csr_rw	3.000s	13.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	94.194us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	38.044us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	17.907us	5	5	100.00
		pattgen_csr_rw	3.000s	13.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	94.194us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	38.044us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	188.774us	20	20	100.00
		pattgen_sec_cm	4.000s	59.125us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	188.774us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.833m	135.802ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			490	520	94.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 25 failures:

Test pattgen_stress_all_with_rand_reset has 25 failures.

1.pattgen_stress_all_with_rand_reset.31216136684955910257615181828937153244456842362856346184492805715122301925477
Line 507, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9312453550 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9312457552 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9312457552 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 9312518158 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.80260593005958412625906460939537860642012793899957576354231625245225146562570
Line 415, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7266270768 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7266276395 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7266276395 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 7266359731 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 23 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 6.pattgen_stress_all_with_rand_reset.61451732882381732514254762409100836846820560495150246462957909111003789154553
    Line 475, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1675556684 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 13.pattgen_stress_all_with_rand_reset.95255034945990760158974515683584033383412691143774806329119829462119483345399
    Line 558, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20445262477 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.