PATTGEN Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	723.197us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	13.695us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	19.164us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	370.318us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	21.140us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	45.131us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	19.164us	20	20	100.00
		pattgen_csr_aliasing	3.000s	21.140us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.617m	5.982ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.767m	2.660ms	50	50	100.00
V2	error	pattgen_error	4.000s	40.949us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.583m	15.847ms	50	50	100.00
V2	alert_test	pattgen_alert_test	5.000s	13.791us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	18.390us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	450.129us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	450.129us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	13.695us	5	5	100.00
		pattgen_csr_rw	4.000s	19.164us	20	20	100.00
		pattgen_csr_aliasing	3.000s	21.140us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	12.769us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	13.695us	5	5	100.00
		pattgen_csr_rw	4.000s	19.164us	20	20	100.00
		pattgen_csr_aliasing	3.000s	21.140us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	12.769us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	310.519us	20	20	100.00
		pattgen_sec_cm	3.000s	58.985us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	310.519us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	22.767m	111.336ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 35 failures:

Test pattgen_stress_all_with_rand_reset has 35 failures.

0.pattgen_stress_all_with_rand_reset.114880443327307650537443271525434187932802526506136223312620710112081562957426
Line 939, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 196775027073 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 196775045449 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 196775045449 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 196775378784 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.26162707260599750433167636072487111786000032276773178424193192238283837117672
Line 436, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7850416001 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7850424347 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7850424347 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 7850497266 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 33 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 1.pattgen_stress_all_with_rand_reset.6226203219804716012753405706046083039773025215059160281474040616219593845613
    Line 656, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32435275212 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 5.pattgen_stress_all_with_rand_reset.39936153565914038714371830749963504546924079122247173683792504045279553106955
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 145780127 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```