PATTGEN Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	333.702us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	13.014us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	8.000s	88.688us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	10.000s	288.836us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	92.102us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	63.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	8.000s	88.688us	20	20	100.00
		pattgen_csr_aliasing	2.000s	92.102us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.717m	8.224ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	2.309ms	50	50	100.00
V2	error	pattgen_error	12.000s	77.003us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.967m	5.601ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	18.451us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	10.621us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	13.000s	427.855us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	13.000s	427.855us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	13.014us	5	5	100.00
		pattgen_csr_rw	8.000s	88.688us	20	20	100.00
		pattgen_csr_aliasing	2.000s	92.102us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	27.209us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	13.014us	5	5	100.00
		pattgen_csr_rw	8.000s	88.688us	20	20	100.00
		pattgen_csr_aliasing	2.000s	92.102us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	27.209us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	51.660us	20	20	100.00
		pattgen_sec_cm	21.000s	37.300us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	51.660us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.233m	423.631ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.91077735825152388135045188909276285117361091343754023455078227179610513914474
Line 522, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8941907586 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8941912353 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8941912353 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 8941962353 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.112962973943229363124710495777016242250795567417093111015738341361224771992377
Line 308, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2693671229 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2693677419 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2693677419 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 2693776320 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 17.pattgen_stress_all_with_rand_reset.22970055925890559275468062953765764342400617856085897817307344444504431759027
    Line 490, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6283239379 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 18.pattgen_stress_all_with_rand_reset.56468958903414461096139045955070095889417553508834475207458296963098432914033
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146146229 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.