PATTGEN Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	86.739us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	12.000s	22.268us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	83.357us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	648.676us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	44.780us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	124.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	83.357us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.780us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.633m	3.950ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.067m	2.744ms	50	50	100.00
V2	error	pattgen_error	8.000s	100.789us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.817m	16.468ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	35.592us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	26.278us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	53.790us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	53.790us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	12.000s	22.268us	5	5	100.00
		pattgen_csr_rw	7.000s	83.357us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.780us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	56.524us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	12.000s	22.268us	5	5	100.00
		pattgen_csr_rw	7.000s	83.357us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.780us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	56.524us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	90.181us	20	20	100.00
		pattgen_sec_cm	2.000s	132.758us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	90.181us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.967m	115.398ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			484	520	93.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.43891763219845163325061456187812273520661663126501602812047330483255650727080
Line 641, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19383084107 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 19383089057 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 19383089057 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 19383173265 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.51484510822889502096831256463024535558986770828979138155084752946247651832797
Line 489, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20988010230 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 20988012021 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 20988012021 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 20988178685 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 31.pattgen_stress_all_with_rand_reset.73160101843443862841046773252036353987495839040651502766388224560727702918772
    Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 180836205 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 36.pattgen_stress_all_with_rand_reset.5558926379857136314505179800264210581665818591623862711369828038540031754643
    Line 460, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23738618236 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 1 more failures.