PATTGEN Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	346.544us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	45.345us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	11.490us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	267.845us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	38.022us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	29.592us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	11.490us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.022us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.883m	7.890ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	5.265ms	50	50	100.00
V2	error	pattgen_error	3.000s	19.219us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.883m	22.427ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	69.176us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	61.358us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	144.047us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	144.047us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	45.345us	5	5	100.00
		pattgen_csr_rw	3.000s	11.490us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.022us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	58.265us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	45.345us	5	5	100.00
		pattgen_csr_rw	3.000s	11.490us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.022us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	58.265us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	174.338us	20	20	100.00
		pattgen_sec_cm	2.000s	36.093us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	174.338us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	33.367m	372.330ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			488	520	93.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

2.pattgen_stress_all_with_rand_reset.47410717373790470821242479868777047222788288134825939740975615839579533956881
Line 319, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1599793602 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1599807850 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1599807850 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 1599963404 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.104954332740681776348469752863597412925651352936921125455164033457679353934668
Line 854, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36167364409 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36167368983 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36167368983 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 36167429589 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 3.pattgen_stress_all_with_rand_reset.26409404201388796194580229305843565002244496033522624601994748046384752888002
    Line 1736, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 293188571205 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 36.pattgen_stress_all_with_rand_reset.84398212202573274286308590769610854617287663561872823171138365290439535056717
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 303437706 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```