PATTGEN Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 16.000s 171.075us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 13.036us 5 5 100.00
V1 csr_rw pattgen_csr_rw 12.000s 27.794us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 705.843us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 211.684us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 8.000s 114.823us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 12.000s 27.794us 20 20 100.00
pattgen_csr_aliasing 3.000s 211.684us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.783m 3.949ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.850m 2.743ms 50 50 100.00
V2 error pattgen_error 4.000s 50.370us 50 50 100.00
V2 stress_all pattgen_stress_all 2.683m 6.466ms 50 50 100.00
V2 alert_test pattgen_alert_test 7.000s 12.911us 50 50 100.00
V2 intr_test pattgen_intr_test 12.000s 45.031us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 14.000s 117.943us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 14.000s 117.943us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 13.036us 5 5 100.00
pattgen_csr_rw 12.000s 27.794us 20 20 100.00
pattgen_csr_aliasing 3.000s 211.684us 5 5 100.00
pattgen_same_csr_outstanding 8.000s 65.856us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 13.036us 5 5 100.00
pattgen_csr_rw 12.000s 27.794us 20 20 100.00
pattgen_csr_aliasing 3.000s 211.684us 5 5 100.00
pattgen_same_csr_outstanding 8.000s 65.856us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 13.000s 287.746us 20 20 100.00
pattgen_sec_cm 3.000s 68.893us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 13.000s 287.746us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 35.050m 111.372ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 490 520 94.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.76 100.00 100.00 100.00 99.06 96.13 -- 100.00 89.95

Failure Buckets

Past Results