PATTGEN Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	174.248us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	14.665us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	22.118us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	2.058ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	70.381us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	25.021us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	22.118us	20	20	100.00
		pattgen_csr_aliasing	3.000s	70.381us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.983m	52.630ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	2.691ms	50	50	100.00
V2	error	pattgen_error	8.000s	53.409us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.800m	5.354ms	50	50	100.00
V2	alert_test	pattgen_alert_test	17.000s	22.841us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	17.478us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	246.998us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	246.998us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	14.665us	5	5	100.00
		pattgen_csr_rw	3.000s	22.118us	20	20	100.00
		pattgen_csr_aliasing	3.000s	70.381us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	14.013us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	14.665us	5	5	100.00
		pattgen_csr_rw	3.000s	22.118us	20	20	100.00
		pattgen_csr_aliasing	3.000s	70.381us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	14.013us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	162.244us	20	20	100.00
		pattgen_sec_cm	2.000s	389.302us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	162.244us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	45.350m	236.879ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			488	520	93.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 29 failures:

Test pattgen_stress_all_with_rand_reset has 29 failures.

1.pattgen_stress_all_with_rand_reset.65861299171468383960840942928276722262929486834425641116972748779031385854703
Line 439, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9574071959 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9574081042 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9574081042 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 9574163514 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.86238529394490471784828056928038313239254262472730868035334900824356672000629
Line 396, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11987160870 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11987175848 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11987175848 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 11987432258 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 27 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 18.pattgen_stress_all_with_rand_reset.17691547621006503752189271909542497960481051866872133501683500340918434322174
    Line 640, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67778216439 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 25.pattgen_stress_all_with_rand_reset.10085699119678327602747689640989996047836274811191053987099216271877490603090
    Line 391, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5061278303 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.