PATTGEN Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	37.617us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	8.000s	18.243us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	29.663us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	12.000s	36.628us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	6.000s	14.376us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	14.000s	38.924us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	29.663us	20	20	100.00
		pattgen_csr_aliasing	6.000s	14.376us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.800m	4.072ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.917m	5.368ms	50	50	100.00
V2	error	pattgen_error	14.000s	16.495us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.683m	10.675ms	50	50	100.00
V2	alert_test	pattgen_alert_test	18.000s	48.446us	50	50	100.00
V2	intr_test	pattgen_intr_test	14.000s	13.555us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	11.000s	777.201us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	11.000s	777.201us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	8.000s	18.243us	5	5	100.00
		pattgen_csr_rw	6.000s	29.663us	20	20	100.00
		pattgen_csr_aliasing	6.000s	14.376us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	110.359us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	8.000s	18.243us	5	5	100.00
		pattgen_csr_rw	6.000s	29.663us	20	20	100.00
		pattgen_csr_aliasing	6.000s	14.376us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	110.359us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	15.000s	252.722us	20	20	100.00
		pattgen_sec_cm	17.000s	251.461us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	15.000s	252.722us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.350m	280.940ms	3	50	6.00
V3		TOTAL			3	50	6.00
		TOTAL			473	520	90.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 42 failures:

Test pattgen_stress_all_with_rand_reset has 42 failures.

0.pattgen_stress_all_with_rand_reset.14295047693136319658495584669580371559706619958720351505647798835261967076492
Line 402, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26516128947 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 26516129202 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 26516129202 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 26516254203 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.92202587244789438313446934177405489611138815257294759965349332862950682113065
Line 598, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32203289362 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 32203310031 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 32203310031 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 32203476695 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 40 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 3.pattgen_stress_all_with_rand_reset.83794370642946339647025191446469828521513531829694548023438954982255764769857
    Line 491, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7414095890 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 17.pattgen_stress_all_with_rand_reset.87387228810704096526266987994674657098242117011176834843713753730632319436
    Line 665, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117476728712 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.