PATTGEN Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	657.295us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	49.873us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	140.986us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	193.776us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	30.445us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	26.882us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	140.986us	20	20	100.00
		pattgen_csr_aliasing	2.000s	30.445us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.967m	44.215ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	5.370ms	50	50	100.00
V2	error	pattgen_error	3.000s	126.220us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.717m	7.405ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	39.120us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	13.646us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	135.089us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	135.089us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	49.873us	5	5	100.00
		pattgen_csr_rw	2.000s	140.986us	20	20	100.00
		pattgen_csr_aliasing	2.000s	30.445us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	100.845us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	49.873us	5	5	100.00
		pattgen_csr_rw	2.000s	140.986us	20	20	100.00
		pattgen_csr_aliasing	2.000s	30.445us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	100.845us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	207.311us	20	20	100.00
		pattgen_sec_cm	3.000s	263.091us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	207.311us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	27.417m	285.486ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

4.pattgen_stress_all_with_rand_reset.112030673300460811393232295669733778250473178167910342444392166252643717093640
Line 639, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12860398706 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 12860400419 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12860400419 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 12860461643 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.111911734248832323999901561380440456499575663753727216324727133459457744369878
Line 676, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 86869508445 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 86869529556 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 86869529556 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 86869904559 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 2.pattgen_stress_all_with_rand_reset.43486605475831104180168992688170537655925769711999496788888117872053412915418
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 235900845 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 19.pattgen_stress_all_with_rand_reset.40231986573004768122032518692692827477801382905886103901094195292782946052841
    Line 609, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24191478547 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 4 more failures.