PATTGEN Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	11.000s	213.165us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	41.208us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	44.769us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	64.191us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	75.097us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	63.422us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	44.769us	20	20	100.00
		pattgen_csr_aliasing	3.000s	75.097us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.917m	15.168ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	3.133ms	50	50	100.00
V2	error	pattgen_error	3.000s	71.559us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.650m	11.061ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	10.378us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	14.893us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	87.850us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	87.850us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	41.208us	5	5	100.00
		pattgen_csr_rw	3.000s	44.769us	20	20	100.00
		pattgen_csr_aliasing	3.000s	75.097us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	14.084us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	41.208us	5	5	100.00
		pattgen_csr_rw	3.000s	44.769us	20	20	100.00
		pattgen_csr_aliasing	3.000s	75.097us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	14.084us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	243.622us	20	20	100.00
		pattgen_sec_cm	3.000s	97.464us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	243.622us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.367m	82.446ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			487	520	93.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.99248529118268374515012658092206928910203208018685309083923333629456263296542
Line 330, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29253311002 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 29253325747 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 29253325747 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 29253525747 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.62405125921112506675616572852742709007900555627012379077125077993066609991093
Line 296, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3598925674 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3598943035 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3598943035 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 3599318038 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 10.pattgen_stress_all_with_rand_reset.71255706023302330685750459013915191008900744601673607932160863004639244171848
    Line 326, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 727165852 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 28.pattgen_stress_all_with_rand_reset.110212651675889057431269135257699539561499782119954503932775490040637284511179
    Line 633, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89679316442 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.