PATTGEN Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	486.939us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	41.158us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	12.058us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.470ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	32.141us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	53.096us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	12.058us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.141us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.933m	15.775ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	9.652ms	50	50	100.00
V2	error	pattgen_error	3.000s	53.664us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.917m	16.957ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	42.915us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	43.463us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	476.231us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	476.231us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	41.158us	5	5	100.00
		pattgen_csr_rw	3.000s	12.058us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.141us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	54.497us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	41.158us	5	5	100.00
		pattgen_csr_rw	3.000s	12.058us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.141us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	54.497us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	48.607us	20	20	100.00
		pattgen_sec_cm	3.000s	70.879us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	48.607us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	46.067m	479.186ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			481	520	92.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 36 failures:

Test pattgen_stress_all_with_rand_reset has 36 failures.

0.pattgen_stress_all_with_rand_reset.25628421048232721582550127690854709683615602516938796306252149615440466842854
Line 301, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5527477539 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5527492350 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5527492350 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 5527761584 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.15427366333657966869460541129753328328375260855102119720760922577596617607998
Line 325, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 671656940 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 671662017 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 671662017 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 671757759 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 34 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 2.pattgen_stress_all_with_rand_reset.84999641622859570911079614612457764544996883608357338656328128906123108490481
    Line 402, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4318028409 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 40.pattgen_stress_all_with_rand_reset.84077789233752328029061004564617737322613278839740688916955205683272222839779
    Line 434, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8237465474 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.