PATTGEN Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	344.920us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	55.702us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	36.587us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	800.307us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.696us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	67.041us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	36.587us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.696us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.850m	32.893ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	2.745ms	50	50	100.00
V2	error	pattgen_error	8.000s	35.591us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.500m	15.984ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	12.593us	50	50	100.00
V2	intr_test	pattgen_intr_test	9.000s	13.069us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	10.000s	372.957us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	10.000s	372.957us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	55.702us	5	5	100.00
		pattgen_csr_rw	4.000s	36.587us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.696us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	74.733us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	55.702us	5	5	100.00
		pattgen_csr_rw	4.000s	36.587us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.696us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	74.733us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	50.601us	20	20	100.00
		pattgen_sec_cm	2.000s	155.965us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	50.601us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	29.400m	295.352ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			481	520	92.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

0.pattgen_stress_all_with_rand_reset.13777623328620385785110643645467650145164623762948128805143080351290061003339
Line 573, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28757106629 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 28757120250 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28757120250 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 28757161916 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.63147358322307539891875078774170846009658622164341171830672909805122522518720
Line 315, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3234199518 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3234207519 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3234207519 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 3234228353 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 37.pattgen_stress_all_with_rand_reset.28961885756554307392852135356642835925837180567144553138008470544247277492816
    Line 439, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11015624429 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 43.pattgen_stress_all_with_rand_reset.100026685239276858081092663771295510711121662104780300190430809490609691535244
    Line 701, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 177257990454 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```