PATTGEN Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 13.000s 103.289us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 189.921us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 39.317us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 4.000s 724.195us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 8.000s 83.059us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 7.000s 48.609us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 39.317us 20 20 100.00
pattgen_csr_aliasing 8.000s 83.059us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 3.017m 16.443ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.717m 2.557ms 50 50 100.00
V2 error pattgen_error 8.000s 36.227us 50 50 100.00
V2 stress_all pattgen_stress_all 4.533m 27.790ms 50 50 100.00
V2 alert_test pattgen_alert_test 12.000s 11.808us 50 50 100.00
V2 intr_test pattgen_intr_test 11.000s 16.768us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 8.000s 61.925us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 8.000s 61.925us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 189.921us 5 5 100.00
pattgen_csr_rw 3.000s 39.317us 20 20 100.00
pattgen_csr_aliasing 8.000s 83.059us 5 5 100.00
pattgen_same_csr_outstanding 12.000s 68.536us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 189.921us 5 5 100.00
pattgen_csr_rw 3.000s 39.317us 20 20 100.00
pattgen_csr_aliasing 8.000s 83.059us 5 5 100.00
pattgen_same_csr_outstanding 12.000s 68.536us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 7.000s 227.974us 20 20 100.00
pattgen_sec_cm 7.000s 220.224us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 7.000s 227.974us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 43.117m 215.347ms 11 50 22.00
V3 TOTAL 11 50 22.00
TOTAL 481 520 92.50

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.76 100.00 100.00 100.00 99.06 96.13 -- 100.00 89.95

Failure Buckets

Past Results