PATTGEN Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	103.289us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	189.921us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	39.317us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	724.195us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	8.000s	83.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	48.609us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	39.317us	20	20	100.00
		pattgen_csr_aliasing	8.000s	83.059us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	3.017m	16.443ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.717m	2.557ms	50	50	100.00
V2	error	pattgen_error	8.000s	36.227us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.533m	27.790ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	11.808us	50	50	100.00
V2	intr_test	pattgen_intr_test	11.000s	16.768us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	61.925us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	61.925us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	189.921us	5	5	100.00
		pattgen_csr_rw	3.000s	39.317us	20	20	100.00
		pattgen_csr_aliasing	8.000s	83.059us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	68.536us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	189.921us	5	5	100.00
		pattgen_csr_rw	3.000s	39.317us	20	20	100.00
		pattgen_csr_aliasing	8.000s	83.059us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	68.536us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	227.974us	20	20	100.00
		pattgen_sec_cm	7.000s	220.224us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	227.974us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	43.117m	215.347ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			481	520	92.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 36 failures:

Test pattgen_stress_all_with_rand_reset has 36 failures.

0.pattgen_stress_all_with_rand_reset.37103180399352466644273372788433605347832545951542813811458423835966384502364
Line 1154, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 72292445091 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 72292448242 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 72292448242 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 72292491721 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.4238139941892224891806825274772204882165056206830996472500795797582544041464
Line 561, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21380808817 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 21380823421 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 21380823421 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 21380945869 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 34 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 2.pattgen_stress_all_with_rand_reset.82342024394929536227257968618930644604891803765555880774947547437032116260518
    Line 737, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81662016616 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 15.pattgen_stress_all_with_rand_reset.28117231727569637740878828435212611709878382634472869567734297883911736309423
    Line 641, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65952241772 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.