PATTGEN Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	2.646ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	35.088us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	15.115us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	940.789us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	28.449us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	100.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	15.115us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.449us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.767m	23.197ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	2.632ms	50	50	100.00
V2	error	pattgen_error	7.000s	17.753us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.000m	4.816ms	50	50	100.00
V2	alert_test	pattgen_alert_test	22.000s	35.705us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	11.302us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	263.260us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	263.260us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	35.088us	5	5	100.00
		pattgen_csr_rw	3.000s	15.115us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.449us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	28.044us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	35.088us	5	5	100.00
		pattgen_csr_rw	3.000s	15.115us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.449us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	28.044us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	82.156us	20	20	100.00
		pattgen_sec_cm	4.000s	221.057us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	82.156us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	35.067m	1.114s	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.89451364027792606601961086761567494211504133762238548275302233989342322792909
Line 292, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 509870821 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 509872364 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 509872364 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 509943792 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.36667792634938664867105331455324855857389097859752022607749497669853678714447
Line 843, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 63335952279 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 63335956348 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 63335956348 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 63336156348 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 28.pattgen_stress_all_with_rand_reset.18416126626827352943601842186636870445381506176821460232068425921602767014414
    Line 304, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 866640417 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 35.pattgen_stress_all_with_rand_reset.3665021143170549270143193707908250550530437003491471819364782101560312729783
    Line 594, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19868194269 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.