PATTGEN Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	661.440us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	16.465us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	18.426us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	776.169us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	29.963us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	42.880us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	18.426us	20	20	100.00
		pattgen_csr_aliasing	2.000s	29.963us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.917m	16.431ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	10.956ms	50	50	100.00
V2	error	pattgen_error	4.000s	29.769us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.967m	11.200ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	23.771us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	28.421us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	106.012us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	106.012us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	16.465us	5	5	100.00
		pattgen_csr_rw	3.000s	18.426us	20	20	100.00
		pattgen_csr_aliasing	2.000s	29.963us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	47.394us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	16.465us	5	5	100.00
		pattgen_csr_rw	3.000s	18.426us	20	20	100.00
		pattgen_csr_aliasing	2.000s	29.963us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	47.394us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	284.042us	20	20	100.00
		pattgen_sec_cm	2.000s	142.011us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	284.042us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	59.900m	655.614ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			488	520	93.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 29 failures:

Test pattgen_stress_all_with_rand_reset has 29 failures.

1.pattgen_stress_all_with_rand_reset.37348756795153938411502343617778995771405082223995218500991993982733723881427
Line 316, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27788438409 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 27788464626 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 27788464626 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 27788750342 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.77198464861999826324824671153311687532693403182909378289804815317513761235000
Line 599, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45774176631 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 45774191687 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 45774191687 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 45774582989 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 27 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 22.pattgen_stress_all_with_rand_reset.114569057210256222797840635144451863939471130429819214825509370841127247046215
    Line 834, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27325027368 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 31.pattgen_stress_all_with_rand_reset.21139113947460691851927852453839544419676658014229468979832401445638901816481
    Line 336, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1152801478 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.