PATTGEN Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	187.720us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	16.050us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	26.525us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	193.166us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	16.238us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	29.450us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	26.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.238us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	4.030ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	5.263ms	50	50	100.00
V2	error	pattgen_error	3.000s	102.798us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.150m	26.775ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	45.524us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	15.241us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	193.206us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	193.206us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	16.050us	5	5	100.00
		pattgen_csr_rw	2.000s	26.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.238us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	330.477us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	16.050us	5	5	100.00
		pattgen_csr_rw	2.000s	26.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.238us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	330.477us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	186.441us	20	20	100.00
		pattgen_sec_cm	3.000s	66.263us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	186.441us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.250m	404.451ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			480	520	92.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.77	100.00	100.00	100.00	99.09	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 36 failures:

Test pattgen_stress_all_with_rand_reset has 36 failures.

0.pattgen_stress_all_with_rand_reset.10708443415222134625135967793213910302562802604044676332714829299711511343771
Line 1522, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 71222996052 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 71223003828 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 71223003828 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 71223103828 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.2135615662376609525035736670022923745074356697496513122578214964017571927158
Line 820, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62567746011 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 62567769171 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 62567769171 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 62567925421 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 34 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 8.pattgen_stress_all_with_rand_reset.110878176171654618086680399207068241978825352593519978919955102680994372607629
    Line 601, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15775250488 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 23.pattgen_stress_all_with_rand_reset.49805330256189556356063831509874321156568785834219574866378906656814053251576
    Line 478, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7756213551 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.