PATTGEN Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 7.000s 132.982us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 43.514us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 36.718us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 63.215us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 54.580us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 97.229us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 36.718us 20 20 100.00
pattgen_csr_aliasing 3.000s 54.580us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.800m 3.951ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.883m 2.635ms 50 50 100.00
V2 error pattgen_error 4.000s 15.199us 50 50 100.00
V2 stress_all pattgen_stress_all 4.283m 26.485ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 13.876us 50 50 100.00
V2 intr_test pattgen_intr_test 8.000s 17.403us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 138.616us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 138.616us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 43.514us 5 5 100.00
pattgen_csr_rw 3.000s 36.718us 20 20 100.00
pattgen_csr_aliasing 3.000s 54.580us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 106.970us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 43.514us 5 5 100.00
pattgen_csr_rw 3.000s 36.718us 20 20 100.00
pattgen_csr_aliasing 3.000s 54.580us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 106.970us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 387.559us 20 20 100.00
pattgen_sec_cm 3.000s 158.993us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 387.559us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 33.550m 149.699ms 11 50 22.00
V3 TOTAL 11 50 22.00
Unmapped tests pattgen_inactive_level 1.383m 10.249ms 49 50 98.00
TOTAL 530 570 92.98

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results