PATTGEN Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	132.982us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	43.514us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	36.718us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	63.215us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	54.580us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	97.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	36.718us	20	20	100.00
		pattgen_csr_aliasing	3.000s	54.580us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.800m	3.951ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	2.635ms	50	50	100.00
V2	error	pattgen_error	4.000s	15.199us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.283m	26.485ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.876us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	17.403us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	138.616us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	138.616us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	43.514us	5	5	100.00
		pattgen_csr_rw	3.000s	36.718us	20	20	100.00
		pattgen_csr_aliasing	3.000s	54.580us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	106.970us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	43.514us	5	5	100.00
		pattgen_csr_rw	3.000s	36.718us	20	20	100.00
		pattgen_csr_aliasing	3.000s	54.580us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	106.970us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	387.559us	20	20	100.00
		pattgen_sec_cm	3.000s	158.993us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	387.559us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	33.550m	149.699ms	11	50	22.00
V3		TOTAL			11	50	22.00
	Unmapped tests	pattgen_inactive_level	1.383m	10.249ms	49	50	98.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

0.pattgen_stress_all_with_rand_reset.50965840348206465223279912540267879316200254476698307983449238796784540793106
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 151604236 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 151607305 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 151607305 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 151689777 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.22393502498108783525496945099486080782844566135539100480057483505815379477849
Line 432, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9155581566 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9155589667 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9155589667 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 9155641752 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 18.pattgen_stress_all_with_rand_reset.63295665596844974984746193772902420416941300766182892554128691621546952654577
    Line 428, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11414156601 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 31.pattgen_stress_all_with_rand_reset.43138513157313555510665079756621284060424925799549221072136266238316335640743
    Line 715, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22396895133 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 11.pattgen_inactive_level.103140946658868561455947858535918840652234312611327222774804834330048804168633
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10249332939 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf83acfd0) == 0x0
  UVM_INFO @ 10249332939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```