PATTGEN Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 5.000s 29.850us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 12.440us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 26.247us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 6.000s 1.153ms 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 2.000s 23.674us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 6.000s 30.428us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 26.247us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.674us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.717m 12.730ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.850m 10.119ms 50 50 100.00
V2 error pattgen_error 12.000s 21.278us 50 50 100.00
V2 stress_all pattgen_stress_all 3.750m 22.373ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 40.078us 50 50 100.00
V2 intr_test pattgen_intr_test 4.000s 18.415us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 38.235us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 38.235us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 12.440us 5 5 100.00
pattgen_csr_rw 3.000s 26.247us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.674us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 21.782us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 12.440us 5 5 100.00
pattgen_csr_rw 3.000s 26.247us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.674us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 21.782us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 90.619us 20 20 100.00
pattgen_sec_cm 3.000s 254.177us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 90.619us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 32.083m 185.347ms 20 50 40.00
V3 TOTAL 20 50 40.00
Unmapped tests pattgen_inactive_level 1.917m 10.015ms 42 50 84.00
TOTAL 532 570 93.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results