PATTGEN Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	29.850us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	12.440us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	26.247us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	1.153ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	23.674us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	6.000s	30.428us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	26.247us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.674us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.717m	12.730ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	10.119ms	50	50	100.00
V2	error	pattgen_error	12.000s	21.278us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.750m	22.373ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	40.078us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	18.415us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	38.235us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	38.235us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	12.440us	5	5	100.00
		pattgen_csr_rw	3.000s	26.247us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.674us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	21.782us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	12.440us	5	5	100.00
		pattgen_csr_rw	3.000s	26.247us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.674us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	21.782us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	90.619us	20	20	100.00
		pattgen_sec_cm	3.000s	254.177us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	90.619us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.083m	185.347ms	20	50	40.00
V3		TOTAL			20	50	40.00
	Unmapped tests	pattgen_inactive_level	1.917m	10.015ms	42	50	84.00
		TOTAL			532	570	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 27 failures:

Test pattgen_stress_all_with_rand_reset has 27 failures.

3.pattgen_stress_all_with_rand_reset.80059085018899863422044744607413840941236125244809110890674076623606766156689
Line 297, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1094048894 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1094049765 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1094049765 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 1094102395 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.78284238209763153492940760482665882596820757893793957908399291833337131561468
Line 485, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10918005079 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 10918007173 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 10918007173 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 10918111343 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 25 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 8 failures:
- Test pattgen_inactive_level has 8 failures.
  - 11.pattgen_inactive_level.59403038742275446178153499221406098654148163507194998428675652511489251969121
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015071679 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5a6ee7d0) == 0x0
  UVM_INFO @ 10015071679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.pattgen_inactive_level.2042817405328779935753467671529542673989254376885384301830590095571363765113
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015265560 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9ed4210) == 0x0
  UVM_INFO @ 10015265560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 2.pattgen_stress_all_with_rand_reset.31571382243024264976791973424940214630645100143057109368448940886457150344575
    Line 442, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10124006209 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 8.pattgen_stress_all_with_rand_reset.2161621935355779506817460961872428943526535696057171569609023666559580455003
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 490855292 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.